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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2Fethmac_defines.v&
Tue, 14 Apr 2026 10:45:01 +0100
FeedCreator 1.7.2
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ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=439
<div><strong>Rev 439 - julius</strong> (45 file(s) modified)</div><div>ORPSoC update<br />
<br />
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A<br />
Ethernet MAC ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mul.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c<br />
julius
Mon, 06 Dec 2010 15:22:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=439
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ORPSoC: Renamed eth core to ethmac (correct name), added drivers ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=409
<div><strong>Rev 409 - julius</strong> (52 file(s) modified)</div><div>ORPSoC: Renamed eth core to ethmac (correct name), added drivers ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v<br />- /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />- /openrisc/trunk/orpsocv2/rtl/verilog/eth<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac<br />- /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/ethmac.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/eth-phy-mii.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/include/ethmac.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/ethmac/Makefile<br />- /openrisc/trunk/orpsocv2/sw/tests/eth<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/eth-phy-mii.h<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/eth-ping.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/open-eth.h<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-rx.c<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-rxtx.c<br />- /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/eth-tx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c<br />
julius
Wed, 03 Nov 2010 13:14:32 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=409
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ORPSoC update - adding support for ORSoC development board, many ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=408
<div><strong>Rev 408 - julius</strong> (295 file(s) modified)</div><div>ORPSoC update - adding support for ORSoC development board, many ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/directControl_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/dpMem_dc_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/endpMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/fifoRTL_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/getPacket_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/HCTxPortArbiter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostcontroller_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMuxBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/hostSlaveMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/lineControlUpdate_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxBit_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processRxByte_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/processTxByte_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/readUSBWireData_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/RxfifoBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/RxFifo_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/rxStatusMonitor_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SCTxPortArbiter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacketArbiter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacketCheckPreamble_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/sendPacket_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SIEReceiver_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SIETransmitter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slavecontroller_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveDirectControl_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveGetPacket_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveRxStatusMonitor_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/slaveSendPacket_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SOFController_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/SOFTransmit_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/speedCtrlMux_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/TxfifoBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/TxFifo_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/updateCRC5_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/updateCRC16_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbConstants_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBHostControlBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostControl_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostControl_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbHostSlave_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbhostslave_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbhost_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSerialInterfaceEngine_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSerialInterfaceEngine_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBSlaveControlBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbSlaveControl_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usbslave_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/USBTxWireArbiter_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usb_hostslave_tb.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/usb_slave_tb.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wb_master_model.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wishBoneBI_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/wishBoneBus_h.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/usbhostslave/writeUSBWireData_simlib.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/wiredelay.v<br />+ /openrisc/trunk/orpsocv2/boards/actel<br />+ /openrisc/trunk/orpsocv2/boards/actel/backend<br />+ /openrisc/trunk/orpsocv2/boards/actel/backend/rtl<br />+ /openrisc/trunk/orpsocv2/boards/actel/backend/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/actel/backend/rtl/verilog/proasic3.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuboard.mkpins<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsoccpuexpio.mkpinassigns<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/orsocexpboard.mkpins<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/run<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/eth_pll.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/gbuf.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/orpsoc_flashROM.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb20.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal25_wb24.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb16.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb20.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb24.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/pll_xtal64_wb30.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/rtl/verilog/reset_buffer.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/orpsoc-testbench-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/synthesis-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/spi_slave.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/arbiter/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/flashrom.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/flashrom/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/gpio.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/gpio/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_constants_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_hostcontrol_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_hostslave_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_serialinterfaceengine_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_slavecontrol_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/usbhostslave_wishbonebus_h.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/README<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/burst_length_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/cke_delay_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/codec.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/copyright.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ctrl_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/dcm_pll.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16.fzm<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_16_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ddr_ff.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/delay.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/egress_fifo.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_adr_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fifo_fill.fzm<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fizzim.pl<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_sdr_16.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/fsm_wb.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/inc_adr.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/latency_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/pre_delay_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/ref_delay_counter_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16.fzm<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/sdr_16_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_counter.xls<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ddr.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_top.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_wb.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/out<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/bootrom.v<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-host.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/include/usbhostslave-slave.h<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-host.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/drivers/usbhostslave/usbhostslave-slave.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/i2c_master_slave-loopback.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/i2c_master_slave/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/usbhostslave-hostsimple.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/tests/usbhostslave/sim/usbhostslave-slavesimple.c<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/out<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/run<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/run/Makefile<br />- /openrisc/trunk/orpsocv2/doc/config.log<br />- /openrisc/trunk/orpsocv2/doc/config.status<br />- /openrisc/trunk/orpsocv2/doc/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_bit_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_byte_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/i2c_master_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/i2c_master_slave/README<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/i2c_master_slave_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_constants_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_hostcontrol_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_hostslave_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_serialinterfaceengine_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_slavecontrol_h.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/usbhostslave_wishbonebus_h.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/simple_spi/simple_spi.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_if.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_sync.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/directControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/dpMem_dc.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/endpMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/fifoMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/fifoRTL.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/getPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/HCTxPortArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostcontroller.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/hostSlaveMuxBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/lineControlUpdate.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processRxBit.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processRxByte.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/processTxByte.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/README<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/readUSBWireData.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/RxFifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/RxfifoBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/rxStatusMonitor.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SCTxPortArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacketArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/sendPacketCheckPreamble.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SIEReceiver.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SIETransmitter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slavecontroller.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveDirectControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveGetPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveRxStatusMonitor.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/slaveSendPacket.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SOFController.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/SOFTransmit.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/speedCtrlMux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/TxFifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/TxfifoBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/updateCRC5.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/updateCRC16.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbhost.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbHostControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBHostControlBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbhostslave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbSerialInterfaceEngine.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbslave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/usbSlaveControl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBSlaveControlBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/USBTxWireArbiter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/wishBoneBI.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/usbhostslave/writeUSBWireData.v<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/spiflash-program.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/eth-phy-mii.h<br />~ /openrisc/trunk/orpsocv2/sw/tests/eth/board/eth-ping.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/eth/board/open-eth.h<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/board/uart-echo.c<br />
julius
Wed, 03 Nov 2010 00:57:09 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=408
-
ORPSoC big upgrade - intermediate check in. Lots still missing. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=403
<div><strong>Rev 403 - julius</strong> (60 file(s) modified)</div><div>ORPSoC big upgrade - intermediate check in. Lots still missing. ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/orpsoc-testbench-defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/timescale.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/timescale.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_txrx.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />+ /openrisc/trunk/orpsocv2/sim/bin/definesgen.inc<br />- /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />- /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S<br />- /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/eth/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c<br />
julius
Mon, 01 Nov 2010 19:26:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=403
-
First checkin of new ORPSoC set up - more to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=360
<div><strong>Rev 360 - julius</strong> (94 file(s) modified)</div><div>First checkin of new ORPSoC set up - more to ...</div>- /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/smii<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/tap<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl<br />- /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines_old.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_register.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/Makefile<br />- /openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth<br />- /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_defines.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_startup<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1k_top<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200<br />- /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top<br />- /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/smii<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/spi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/raminfr.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart16550.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_wb.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_sdram_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/wb_switch_b3<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/out<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />
julius
Fri, 10 Sep 2010 17:51:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2Fverilog%2Finclude%2F&rev=360
-
ORPSoCv2 updates: cycle accurate profiling, ELF loading
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=51
<div><strong>Rev 51 - julius</strong> (17 file(s) modified)</div><div>ORPSoCv2 updates: cycle accurate profiling, ELF loading</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/except.S<br />~ /openrisc/trunk/orpsocv2/sw/support/time.c<br />
julius
Thu, 01 Oct 2009 14:17:18 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=51
-
Checking in ORPSoCv2
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=6
<div><strong>Rev 6 - julius</strong> (307 file(s) modified)</div><div>Checking in ORPSoCv2</div>+ /openrisc/trunk/orpsocv2<br />+ /openrisc/trunk/orpsocv2/backend<br />+ /openrisc/trunk/orpsocv2/backend/gbuf.v<br />+ /openrisc/trunk/orpsocv2/backend/sim_lib.v<br />+ /openrisc/trunk/orpsocv2/bench<br />+ /openrisc/trunk/orpsocv2/bench/sysc<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/verilog<br />+ /openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/timescale.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v<br />+ /openrisc/trunk/orpsocv2/rtl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_registers.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_crc32_d1.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines_old.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_register.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_clockgen.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_crc.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_fifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_maccontrol.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_macstatus.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_miim.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_outputcontrol.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_random.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_receivecontrol.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_register.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_registers.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxaddrcheck.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxcounters.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxethmac.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxstatem.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_shiftreg.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_spram_256x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_transmitcontrol.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txcounters.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txethmac.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txstatem.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/filer<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/TODO<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/xilinx_dist_ram_16x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_clgen.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_shift.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top/or1k_top.h<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top/or1k_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_alu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_amultp2_32x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cfgr.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cpu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dc_fsm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dc_ram.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dc_tag.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dmmu_tlb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dmmu_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dpram.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dpram_32x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dpram_256x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_freeze.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_genpc.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_gmultp2_32x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_fsm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_ram.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_tag.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_if.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_immu_tlb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_immu_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_iwb_biu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_lsu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_mem2reg.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_mult_mac.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_operandmuxes.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_pic.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_pm.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_qmem_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_reg2mem.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_rf.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_rfram_generic.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sb_fifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_32x24.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_64x14.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_64x22.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_64x24.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_128x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_256x21.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_512x20.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_1024x8.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_1024x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_1024x32_bw.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_2048x8.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_2048x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_spram_2048x32_bw.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sprs.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_top_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_tpram_32x32.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_tt.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_wbmux.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_wb_biu.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_xcv_ram32x8d.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/copyright.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_buffers.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/generic_gbuf.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_sync.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/tmp.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/raminfr.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_debug_if.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_receiver.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_regs.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_rfifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_sync_flops.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_tfifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_transmitter.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_wb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/delay.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/fizzim.pl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/Makefile<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_16_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_fifo.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.fzm<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm16.fzm<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_inst.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/intercon.vm<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v<br />+ /openrisc/trunk/orpsocv2/sim<br />+ /openrisc/trunk/orpsocv2/sim/bin<br />+ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />+ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />+ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />+ /openrisc/trunk/orpsocv2/sim/run<br />+ /openrisc/trunk/orpsocv2/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/sw<br />+ /openrisc/trunk/orpsocv2/sw/basic<br />+ /openrisc/trunk/orpsocv2/sw/basic/.hex<br />+ /openrisc/trunk/orpsocv2/sw/basic/basic.S<br />+ /openrisc/trunk/orpsocv2/sw/basic/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/cbasic<br />+ /openrisc/trunk/orpsocv2/sw/cbasic/cbasic.c<br />+ /openrisc/trunk/orpsocv2/sw/cbasic/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/cust<br />+ /openrisc/trunk/orpsocv2/sw/cust/cust.c<br />+ /openrisc/trunk/orpsocv2/sw/cust/cust.txt<br />+ /openrisc/trunk/orpsocv2/sw/cust/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/dhry<br />+ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c<br />+ /openrisc/trunk/orpsocv2/sw/dhry/dhry.h<br />+ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/except<br />+ /openrisc/trunk/orpsocv2/sw/except/except_test.c<br />+ /openrisc/trunk/orpsocv2/sw/except/except_test_s.S<br />+ /openrisc/trunk/orpsocv2/sw/except/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/icm<br />+ /openrisc/trunk/orpsocv2/sw/icm/icm.S<br />+ /openrisc/trunk/orpsocv2/sw/icm/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/mmu<br />+ /openrisc/trunk/orpsocv2/sw/mmu/except.S<br />+ /openrisc/trunk/orpsocv2/sw/mmu/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/mmu/mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/mmu/mmu_asm.S<br />+ /openrisc/trunk/orpsocv2/sw/mul<br />+ /openrisc/trunk/orpsocv2/sw/mul/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/mul/mul.c<br />+ /openrisc/trunk/orpsocv2/sw/support<br />+ /openrisc/trunk/orpsocv2/sw/support/board.h<br />+ /openrisc/trunk/orpsocv2/sw/support/except.S<br />+ /openrisc/trunk/orpsocv2/sw/support/int.c<br />+ /openrisc/trunk/orpsocv2/sw/support/int.h<br />+ /openrisc/trunk/orpsocv2/sw/support/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/support/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/support/mc.h<br />+ /openrisc/trunk/orpsocv2/sw/support/orp.cfg<br />+ /openrisc/trunk/orpsocv2/sw/support/orp.cfg.old.org<br />+ /openrisc/trunk/orpsocv2/sw/support/orp.ld<br />+ /openrisc/trunk/orpsocv2/sw/support/reset.S<br />+ /openrisc/trunk/orpsocv2/sw/support/spr_defs.h<br />+ /openrisc/trunk/orpsocv2/sw/support/support.c<br />+ /openrisc/trunk/orpsocv2/sw/support/support.h<br />+ /openrisc/trunk/orpsocv2/sw/support/uart.c<br />+ /openrisc/trunk/orpsocv2/sw/support/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/support/vfnprintf.c<br />+ /openrisc/trunk/orpsocv2/sw/support/vfnprintf.h<br />+ /openrisc/trunk/orpsocv2/sw/support/virtex.tim<br />+ /openrisc/trunk/orpsocv2/sw/syscall<br />+ /openrisc/trunk/orpsocv2/sw/syscall/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/syscall/syscall.S<br />+ /openrisc/trunk/orpsocv2/sw/tick<br />+ /openrisc/trunk/orpsocv2/sw/tick/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tick/tick.S<br />+ /openrisc/trunk/orpsocv2/sw/uart<br />+ /openrisc/trunk/orpsocv2/sw/uart/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/uart/uart.c<br />+ /openrisc/trunk/orpsocv2/sw/uart/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/utils<br />+ /openrisc/trunk/orpsocv2/sw/utils/bin2c.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/bin2flimg.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/bin2hex.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/bin2srec.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/loader.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/utils/marksec<br />+ /openrisc/trunk/orpsocv2/sw/utils/merge2srec<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/ansidecl.h<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/bfd.h<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/dis-asm.h<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/example_input<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-dis.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-opc.c<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32.h<br />+ /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/symcat.h<br />
julius
Thu, 21 May 2009 21:32:57 +0100
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