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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2FMakefile& Mon, 18 May 2026 09:09:47 +0100 FeedCreator 1.7.2 ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=397 <div>Rev 397 - julius (44 file(s) modified)</div><div>ORPSoCv2: doc/ path added, with Texinfo documentation. Still a work ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/Makefile ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v + /openrisc/trunk/orpsocv2/doc + /openrisc/trunk/orpsocv2/doc/aclocal.m4 + /openrisc/trunk/orpsocv2/doc/autom4te.cache + /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.0 + /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.1 + /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.2 + /openrisc/trunk/orpsocv2/doc/autom4te.cache/requests + /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.0 + /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.1 + /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.2 + /openrisc/trunk/orpsocv2/doc/config.log + /openrisc/trunk/orpsocv2/doc/config.status + /openrisc/trunk/orpsocv2/doc/config.texi + /openrisc/trunk/orpsocv2/doc/configure + /openrisc/trunk/orpsocv2/doc/configure.in + /openrisc/trunk/orpsocv2/doc/fdl-1.2.texi + /openrisc/trunk/orpsocv2/doc/install-sh + /openrisc/trunk/orpsocv2/doc/Makefile + /openrisc/trunk/orpsocv2/doc/Makefile.am + /openrisc/trunk/orpsocv2/doc/Makefile.in + /openrisc/trunk/orpsocv2/doc/missing + /openrisc/trunk/orpsocv2/doc/orpsoc.texi + /openrisc/trunk/orpsocv2/doc/texinfo.tex ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.c ~ /openrisc/trunk/orpsocv2/sw/apps/dhry/Makefile ~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile ~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/Makefile ~ /openrisc/trunk/orpsocv2/sw/Makefile.inc + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S ~ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c julius Sat, 30 Oct 2010 13:51:16 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=397 ORPSoCv2 software rearrangement in progress. Basic tests should now run ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=393 <div>Rev 393 - julius (131 file(s) modified)</div><div>ORPSoCv2 software rearrangement in progress. Basic tests should now run ...</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile + /openrisc/trunk/orpsocv2/sw/apps + /openrisc/trunk/orpsocv2/sw/apps/dhry + /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.h + /openrisc/trunk/orpsocv2/sw/apps/spiflash + /openrisc/trunk/orpsocv2/sw/apps/testfloat + /openrisc/trunk/orpsocv2/sw/board + /openrisc/trunk/orpsocv2/sw/board/include + /openrisc/trunk/orpsocv2/sw/board/include/board.h ~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile - /openrisc/trunk/orpsocv2/sw/dhry + /openrisc/trunk/orpsocv2/sw/drivers + /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave + /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/i2c_master_slave.c + /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include + /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include/i2c_master_slave.h + /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/Makefile + /openrisc/trunk/orpsocv2/sw/drivers/or1200 + /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S + /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c + /openrisc/trunk/orpsocv2/sw/drivers/or1200/include + /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h + /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h + /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/spr-defs.h + /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c + /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld + /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-mmu.S + /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c + /openrisc/trunk/orpsocv2/sw/drivers/simple-spi + /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include + /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include/simple-spi.h + /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/Makefile + /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c + /openrisc/trunk/orpsocv2/sw/drivers/uart + /openrisc/trunk/orpsocv2/sw/drivers/uart/include + /openrisc/trunk/orpsocv2/sw/drivers/uart/include/uart.h + /openrisc/trunk/orpsocv2/sw/drivers/uart/Makefile + /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c - /openrisc/trunk/orpsocv2/sw/include/board.h - /openrisc/trunk/orpsocv2/sw/include/dhry.h - /openrisc/trunk/orpsocv2/sw/include/int.h - /openrisc/trunk/orpsocv2/sw/include/or32-utils.h - /openrisc/trunk/orpsocv2/sw/include/printf.h - /openrisc/trunk/orpsocv2/sw/include/simple-spi.h - /openrisc/trunk/orpsocv2/sw/include/spr-defs.h - /openrisc/trunk/orpsocv2/sw/include/uart.h + /openrisc/trunk/orpsocv2/sw/lib + /openrisc/trunk/orpsocv2/sw/lib/include + /openrisc/trunk/orpsocv2/sw/lib/include/cpu-utils.h + /openrisc/trunk/orpsocv2/sw/lib/include/lib-utils.h + /openrisc/trunk/orpsocv2/sw/lib/include/printf.h + /openrisc/trunk/orpsocv2/sw/lib/lib-utils.c + /openrisc/trunk/orpsocv2/sw/lib/Makefile + /openrisc/trunk/orpsocv2/sw/lib/printf.c ~ /openrisc/trunk/orpsocv2/sw/Makefile.inc - /openrisc/trunk/orpsocv2/sw/or1200/Makefile - /openrisc/trunk/orpsocv2/sw/or1200/or1200-cbasic.c - /openrisc/trunk/orpsocv2/sw/or1200/or1200-dctest.c - /openrisc/trunk/orpsocv2/sw/or1200/or1200-div.c - /openrisc/trunk/orpsocv2/sw/or1200/or1200-float.c - /openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c - /openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-basic.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-except.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-fp.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-linkregtest.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-mac.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S - /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-ticksyscall.S - /openrisc/trunk/orpsocv2/sw/sdram/Makefile - /openrisc/trunk/orpsocv2/sw/sdram/sdram-bankrows.c - /openrisc/trunk/orpsocv2/sw/sdram/sdram-banks.c - /openrisc/trunk/orpsocv2/sw/sdram/sdram-board-rows.c - /openrisc/trunk/orpsocv2/sw/sdram/sdram-cols.c - /openrisc/trunk/orpsocv2/sw/sdram/sdram-rows.c - /openrisc/trunk/orpsocv2/sw/spi/Makefile - /openrisc/trunk/orpsocv2/sw/spi/spi-interrupt.c - /openrisc/trunk/orpsocv2/sw/spi/spi-simple.c - /openrisc/trunk/orpsocv2/sw/spiflash - /openrisc/trunk/orpsocv2/sw/support/crt0.S - /openrisc/trunk/orpsocv2/sw/support/exceptions.c - /openrisc/trunk/orpsocv2/sw/support/int.c - /openrisc/trunk/orpsocv2/sw/support/or32-utils.c - /openrisc/trunk/orpsocv2/sw/support/or32.ld - /openrisc/trunk/orpsocv2/sw/support/or1200-mmu.S - /openrisc/trunk/orpsocv2/sw/support/printf.c - /openrisc/trunk/orpsocv2/sw/support/simple-spi.c - /openrisc/trunk/orpsocv2/sw/support/uart.c - /openrisc/trunk/orpsocv2/sw/testfloat + /openrisc/trunk/orpsocv2/sw/tests + /openrisc/trunk/orpsocv2/sw/tests/or1200 + /openrisc/trunk/orpsocv2/sw/tests/or1200/board + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/Makefile + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-simple.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S + /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S + /openrisc/trunk/orpsocv2/sw/tests/sdram + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/Makefile + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-banks.c + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c + /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram.h + /openrisc/trunk/orpsocv2/sw/tests/spi + /openrisc/trunk/orpsocv2/sw/tests/spi/sim + /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile + /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c + /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c + /openrisc/trunk/orpsocv2/sw/tests/uart + /openrisc/trunk/orpsocv2/sw/tests/uart/sim + /openrisc/trunk/orpsocv2/sw/tests/uart/sim/Makefile + /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c + /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c + /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-simple.c - /openrisc/trunk/orpsocv2/sw/uart/Makefile - /openrisc/trunk/orpsocv2/sw/uart/uart-echo.c - /openrisc/trunk/orpsocv2/sw/uart/uart-interrupt.c - /openrisc/trunk/orpsocv2/sw/uart/uart-simple.c julius Wed, 27 Oct 2010 14:30:36 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=393 ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=363 <div>Rev 363 - julius (38 file(s) modified)</div><div>ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile julius Sun, 12 Sep 2010 07:57:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=363 ORPSoCv2 verilator building working again. Board build fixes to follow https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=362 <div>Rev 362 - julius (7 file(s) modified)</div><div>ORPSoCv2 verilator building working again. Board build fixes to follow</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile julius Fri, 10 Sep 2010 22:42:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=362 First checkin of new ORPSoC set up - more to ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=360 <div>Rev 360 - julius (94 file(s) modified)</div><div>First checkin of new ORPSoC set up - more to ...</div>- /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v - /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v - /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v - /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v - /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v - /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v - /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v - /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/cy7c1354.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ddr2_model.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_phy_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/eth_stim.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/ml501_testbench_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/WireDelay.v - /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_top - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200 - /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb - /openrisc/trunk/orpsocv2/rtl/verilog/components/smii - /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl - /openrisc/trunk/orpsocv2/rtl/verilog/components/tap - /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550 - /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus - /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3 - /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_sdram_ctrl - /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3 + /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu_registers.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_crc32_d1.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_defines_old.v + /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_register.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb_defines.v - /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/Makefile - /openrisc/trunk/orpsocv2/rtl/verilog/dummy_slave.v + /openrisc/trunk/orpsocv2/rtl/verilog/eth - /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include + /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/tap_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/include/uart_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap + /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v - /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_defines.v - /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/tap_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/or1k_startup + /openrisc/trunk/orpsocv2/rtl/verilog/or1k_top + /openrisc/trunk/orpsocv2/rtl/verilog/or1200 - /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top - /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb + /openrisc/trunk/orpsocv2/rtl/verilog/smii + /openrisc/trunk/orpsocv2/rtl/verilog/spi_ctrl + /openrisc/trunk/orpsocv2/rtl/verilog/uart16550 - /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/Makefile ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/raminfr.v + /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart16550.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_debug_if.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_sync_flops.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v - /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_wb.v - /openrisc/trunk/orpsocv2/rtl/verilog/uart_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus - /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3 + /openrisc/trunk/orpsocv2/rtl/verilog/wb_sdram_ctrl + /openrisc/trunk/orpsocv2/rtl/verilog/wb_switch_b3 ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile + /openrisc/trunk/orpsocv2/sim/out ~ /openrisc/trunk/orpsocv2/sw/Makefile.inc julius Fri, 10 Sep 2010 17:51:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=360 Added new simple MAC test to ORPSoC test suite: * orpsocv2/sw/or1200asm/or1200asm-mac.S: ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=356 <div>Rev 356 - julius (7 file(s) modified)</div><div>Added new simple MAC test to ORPSoC test suite: * orpsocv2/sw/or1200asm/or1200asm-mac.S: ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c ~ /openrisc/trunk/orpsocv2/sw/include/or1200-defines.h + /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-mac.S julius Thu, 09 Sep 2010 23:41:28 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=356 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=354 <div>Rev 354 - julius (15 file(s) modified)</div><div>Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut * sw/support/crt0.S: Tick timer ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v ~ /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg ~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c - /openrisc/trunk/orpsocv2/sw/dhry/dhry.h ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile ~ /openrisc/trunk/orpsocv2/sw/include/board.h + /openrisc/trunk/orpsocv2/sw/include/dhry.h ~ /openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c ~ /openrisc/trunk/orpsocv2/sw/support/crt0.S julius Wed, 08 Sep 2010 18:00:48 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=354 OR1200 with icarus fixed up. MMu test fix, remove testfloat ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=351 <div>Rev 351 - julius (14 file(s) modified)</div><div>OR1200 with icarus fixed up. MMu test fix, remove testfloat ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_dc_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3 + /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3 + /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_switch_b3/wb_switch_b3.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr ~ /openrisc/trunk/orpsocv2/sw/include/spr-defs.h ~ /openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c - /openrisc/trunk/orpsocv2/sw/testfloat/testfloat.elf julius Tue, 07 Sep 2010 17:46:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=351 First stage of ORPSoCv2 update - more to come https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=348 <div>Rev 348 - julius (20 file(s) modified)</div><div>First stage of ORPSoCv2 update - more to come</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2 ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr - /openrisc/trunk/orpsocv2/sw/basic - /openrisc/trunk/orpsocv2/sw/cbasic - /openrisc/trunk/orpsocv2/sw/cust - /openrisc/trunk/orpsocv2/sw/except - /openrisc/trunk/orpsocv2/sw/fpu - /openrisc/trunk/orpsocv2/sw/icm - /openrisc/trunk/orpsocv2/sw/mmu - /openrisc/trunk/orpsocv2/sw/mul - /openrisc/trunk/orpsocv2/sw/support - /openrisc/trunk/orpsocv2/sw/syscall - /openrisc/trunk/orpsocv2/sw/tick - /openrisc/trunk/orpsocv2/sw/uart julius Tue, 07 Sep 2010 13:34:55 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=348 Fixed typo in Silos workaround script https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=78 <div>Rev 78 - rherveille (1 file(s) modified)</div><div>Fixed typo in Silos workaround script</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile rherveille Wed, 07 Apr 2010 18:32:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=78 Added support for Silvaco's Silos simulator Added workaround for Silos's exit ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=77 <div>Rev 77 - rherveille (1 file(s) modified)</div><div>Added support for Silvaco's Silos simulator Added workaround for Silos's exit ...</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile rherveille Wed, 07 Apr 2010 18:15:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=77 ORPSoC cycle accurate trace generation now compatible with latest version ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=70 <div>Rev 70 - julius (3 file(s) modified)</div><div>ORPSoC cycle accurate trace generation now compatible with latest version ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr julius Fri, 19 Feb 2010 04:22:14 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=70 ORPSoC xilinx ml501 board update - added ethernet eupport and ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=69 <div>Rev 69 - julius (31 file(s) modified)</div><div>ORPSoC xilinx ml501 board update - added ethernet eupport and ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.c + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth.ld + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/eth_reset.S + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/except.S + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/mii.h + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth/open_eth.h ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/filer - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/Makefile - /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/TODO ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile julius Fri, 19 Feb 2010 03:25:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=69 Fixed up a couple of Makefile things in ORPSoCv2 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=68 <div>Rev 68 - julius (2 file(s) modified)</div><div>Fixed up a couple of Makefile things in ORPSoCv2</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr julius Tue, 16 Feb 2010 11:47:17 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=68 New synthesizable builds of ORPSoC - first for the Xilinx ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=67 <div>Rev 67 - julius (107 file(s) modified)</div><div>New synthesizable builds of ORPSoC - first for the Xilinx ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/cy7c1354.v + /openrisc/trunk/orpsocv2/bench/verilog/ddr2_model.v ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v + /openrisc/trunk/orpsocv2/boards + /openrisc/trunk/orpsocv2/boards/tools.inc + /openrisc/trunk/orpsocv2/boards/xilinx + /openrisc/trunk/orpsocv2/boards/xilinx/ml501 + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ddr2_model_parameters.vh + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/ml501_testbench_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/WireDelay.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/par/ml501_xst.ucf + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_chipscope.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_ctrl.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_idelay_ctrl.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_infrastructure.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mem_if_top.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_mig.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_calib.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_ctl_io.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dm_iob.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dqs_iob.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_dq_iob.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_init.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_io.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_top.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_phy_write.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_top.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_addr_fifo.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_rd.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_top.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig/ddr2_usr_wr.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/dummy_slave.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/eth_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_params.vh + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if.v.prev + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_ddr2_wb_if_cache.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_gpio.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_mc.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ml501_startup.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/or1200_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/reset_debounce.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ssram_controller.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/uart_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/usr_rst.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_conbus_defines.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/wb_lfsr.v + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/modelsim.scr + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/run/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board.h + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.c + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot.ld + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/boot_reset.S + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.c + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio.ld + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/gpio_reset.S + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.c + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest.ld + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest/memtest_reset.S + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/Makefile + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501.xcf + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_ddr2_wb_if_cache.ngc + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/ml501_xst.tpl + /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/timescale.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_defines.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_clgen.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_shift.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/spi_flash_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl + /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_clgen.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_shift.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/spi_ctrl/spi_flash_top.v - /openrisc/trunk/orpsocv2/rtl/verilog/components/tap/tap.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr ~ /openrisc/trunk/orpsocv2/sw/support/reset.S ~ /openrisc/trunk/orpsocv2/sw/support/uart.c ~ /openrisc/trunk/orpsocv2/sw/support/uart.h ~ /openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c julius Tue, 16 Feb 2010 08:58:52 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=67 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=66 <div>Rev 66 - julius (8 file(s) modified)</div><div>Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/support.c julius Wed, 27 Jan 2010 10:49:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=66 Trying to fix the system c model jtagsc.h checkout problem, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=64 <div>Rev 64 - julius (10 file(s) modified)</div><div>Trying to fix the system c model jtagsc.h checkout problem, ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h - /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h + /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile julius Wed, 20 Jan 2010 09:36:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=64 Finally adding RSP server to cycle accurate model, based on ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=63 <div>Rev 63 - julius (49 file(s) modified)</div><div>Finally adding RSP server to cycle accurate model, based on ...</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h + /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h + /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h + /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h + /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h + /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h + /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make + /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile + /openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp ~ /openrisc/trunk/orpsocv2/sw/utils/Makefile julius Sun, 10 Jan 2010 12:31:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=63 ORPSoC2 update - added fpu and implemented in processor, also ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=58 <div>Rev 58 - julius (49 file(s) modified)</div><div>ORPSoC2 update - added fpu and implemented in processor, also ...</div>+ /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/add_sub27.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/div_r2.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/except.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fcmp.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/fpu.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/mul_r2.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/post_norm.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/fpu/pre_norm_fmul.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_fpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_freeze.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_wbmux.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/icarus.scr ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr ~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr ~ /openrisc/trunk/orpsocv2/sw/basic/basic.S ~ /openrisc/trunk/orpsocv2/sw/cbasic/cbasic.c ~ /openrisc/trunk/orpsocv2/sw/cust/cust.c ~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile ~ /openrisc/trunk/orpsocv2/sw/eth/eth-basic.c ~ /openrisc/trunk/orpsocv2/sw/eth/eth-int.c ~ /openrisc/trunk/orpsocv2/sw/eth/except.S ~ /openrisc/trunk/orpsocv2/sw/except/except_test.c + /openrisc/trunk/orpsocv2/sw/fpu + /openrisc/trunk/orpsocv2/sw/fpu/fpu.S + /openrisc/trunk/orpsocv2/sw/fpu/Makefile ~ /openrisc/trunk/orpsocv2/sw/icm/icm.S ~ /openrisc/trunk/orpsocv2/sw/mul/Makefile ~ /openrisc/trunk/orpsocv2/sw/mul/mul.c ~ /openrisc/trunk/orpsocv2/sw/support/except.S + /openrisc/trunk/orpsocv2/sw/support/fp.c ~ /openrisc/trunk/orpsocv2/sw/support/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/spr_defs.h ~ /openrisc/trunk/orpsocv2/sw/support/support.c ~ /openrisc/trunk/orpsocv2/sw/support/support.h + /openrisc/trunk/orpsocv2/sw/support/syscall.c ~ /openrisc/trunk/orpsocv2/sw/uart/Makefile ~ /openrisc/trunk/orpsocv2/sw/uart/uart.c julius Sun, 29 Nov 2009 16:46:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=58 ORPSoC execution logs created by event sim and cycle accurate ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=57 <div>Rev 57 - julius (4 file(s) modified)</div><div>ORPSoC execution logs created by event sim and cycle accurate ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile julius Tue, 24 Nov 2009 12:48:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsim%2Fbin%2F&rev=57

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