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https://opencores.org/websvn//websvn/revision?repname=or1k&path=%2For1k%2Ftrunk%2Frc203soc%2Fsyn%2F&rev=1765
<div><strong>Rev 1765 - root</strong> (267 file(s) modified)</div><div>...</div>- /branches<br />+ /or1k<br />+ /or1k/branches<br />+ /or1k/tags<br />+ /or1k/trunk<br />- /tags<br />- /trunk<br />+ /web_uploads<br />+ /web_uploads/arch.gif<br />+ /web_uploads/ats<br />+ /web_uploads/ats/build_binutils.status<br />+ /web_uploads/ats/build_binutils.txt<br />+ /web_uploads/ats/build_gdb.status<br />+ /web_uploads/ats/build_gdb.txt<br />+ /web_uploads/ats/build_newlib_gcc.status<br />+ /web_uploads/ats/build_newlib_gcc.txt<br />+ /web_uploads/ats/build_or1ksim.status<br />+ /web_uploads/ats/build_or1ksim.txt<br />+ /web_uploads/ats/build_uclibc.status<br />+ /web_uploads/ats/build_uclibc.txt<br />+ /web_uploads/ats/build_uclinux.status<br />+ /web_uploads/ats/checkout_binutils.txt<br />+ /web_uploads/ats/checkout_gdb.txt<br />+ /web_uploads/ats/checkout_newlib_gcc.txt<br />+ /web_uploads/ats/checkout_or1ksim.txt<br />+ /web_uploads/ats/checkout_uclibc.txt<br />+ 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root
Tue, 10 Mar 2009 22:46:37 +0100
https://opencores.org/websvn//websvn/revision?repname=or1k&path=%2For1k%2Ftrunk%2Frc203soc%2Fsyn%2F&rev=1765
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Firt import of OR1200 over Celoxica RC203 platform
https://opencores.org/websvn//websvn/revision?repname=or1k&path=%2For1k%2Ftrunk%2Frc203soc%2Fsyn%2F&rev=1327
<div><strong>Rev 1327 - jcastillo</strong> (271 file(s) modified)</div><div>Firt import of OR1200 over Celoxica RC203 platform</div>+ /trunk/rc203soc<br />+ /trunk/rc203soc/backend<br />+ /trunk/rc203soc/backend/xilinx<br />+ /trunk/rc203soc/backend/xilinx/soc.ucf<br />+ /trunk/rc203soc/bench<br />+ /trunk/rc203soc/bench/models<br />+ /trunk/rc203soc/bench/models/zbtram.v<br />+ /trunk/rc203soc/bench/verilog<br />+ /trunk/rc203soc/bench/verilog/rc203_test.v<br />+ /trunk/rc203soc/rtl<br />+ /trunk/rc203soc/rtl/verilog<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface/bench<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/cpu_behavioral.v<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/dbg_tb.v<br />+ /trunk/rc203soc/rtl/verilog/dbg_interface/bench/verilog/timescale.v<br />+ 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/trunk/rc203soc/rtl/verilog/or1200/doc<br />+ /trunk/rc203soc/rtl/verilog/or1200/doc/or1200_spec.doc<br />+ /trunk/rc203soc/rtl/verilog/or1200/doc/or1200_spec.pdf<br />+ /trunk/rc203soc/rtl/verilog/or1200/lib<br />+ /trunk/rc203soc/rtl/verilog/or1200/lib/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/bin<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/bin/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/bin/run_lint<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/log<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/log/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/run<br />+ /trunk/rc203soc/rtl/verilog/or1200/lint/run/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_alu.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_cpu.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_du.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_except.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_freeze.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_genpc.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_if.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_lsu.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_pic.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_pm.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_rf.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sb.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_sprs.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_top.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_tt.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/or1200_xcv_ram32x8d.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/rtl/verilog/timescale.v<br />+ /trunk/rc203soc/rtl/verilog/or1200/sim<br />+ /trunk/rc203soc/rtl/verilog/or1200/sim/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/read_design.inc<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/run_syn<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/bin/top.scr<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/log<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/log/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/out<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/out/README<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/run<br />+ /trunk/rc203soc/rtl/verilog/or1200/syn/synopsys/run/README<br />+ /trunk/rc203soc/rtl/verilog/rc203<br />+ /trunk/rc203soc/rtl/verilog/rc203/rc203_romcontroller.v<br />+ /trunk/rc203soc/rtl/verilog/rc203/rc203_zbtcontroller.v<br />+ /trunk/rc203soc/rtl/verilog/soc.v<br />+ /trunk/rc203soc/rtl/verilog/tc_top.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/readme.txt<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/test_cases<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/test_cases/uart_int.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_device.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_device_utilities.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_log.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_test.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench_defines.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_testbench_utilities.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/uart_wb_utilities.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/vapi.log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_mast.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_master_model.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/verilog/wb_model_defines.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/vhdl<br />+ /trunk/rc203soc/rtl/verilog/uart16550/bench/vhdl/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/Doc<br />+ /trunk/rc203soc/rtl/verilog/uart16550/Doc/src<br />+ /trunk/rc203soc/rtl/verilog/uart16550/Doc/src/UART_spec.doc<br />+ /trunk/rc203soc/rtl/verilog/uart16550/fv<br />+ /trunk/rc203soc/rtl/verilog/uart16550/fv/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/bin<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/bin/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/log/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/out<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/out/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/run<br />+ /trunk/rc203soc/rtl/verilog/uart16550/lint/run/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/timescale.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_defines.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_fifo.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_receiver.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_regs.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_top.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_transmitter.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog-backup/uart_wb.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/raminfr.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/timescale.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_defines.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_receiver.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_regs.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_top.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/verilog/uart_wb.v<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/vhdl<br />+ /trunk/rc203soc/rtl/verilog/uart16550/rtl/vhdl/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/bin<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/bin/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/log/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/out<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/out/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/run<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/run/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/src<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/gate_sim/src/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin/nc.scr<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/bin/sim.tcl<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/uart_interrupts_report.log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/log/uart_interrupts_verbose.log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/out<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/out/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_signalscan<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_sim<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/run/run_sim.scr<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/src<br />+ /trunk/rc203soc/rtl/verilog/uart16550/sim/rtl_sim/src/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/bin<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/bin/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/log<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/log/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/out<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/out/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/run<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/run/.keepme<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/src<br />+ /trunk/rc203soc/rtl/verilog/uart16550/syn/src/.keepme<br />+ /trunk/rc203soc/syn<br />+ /trunk/rc203soc/syn/RAMB4_S4.v<br />+ /trunk/rc203soc/syn/RAMB4_S16.v<br />+ /trunk/rc203soc/syn/RAMB4_S16_S16.v<br />
jcastillo
Mon, 13 Dec 2004 17:16:29 +0100
https://opencores.org/websvn//websvn/revision?repname=or1k&path=%2For1k%2Ftrunk%2Frc203soc%2Fsyn%2F&rev=1327
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