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<div><strong>Rev 5 - sergeykhbr</strong> (449 file(s) modified)</div><div>[*] Merge with git repository<br />
[*] Project structure changed<br />
[+] Add new ...</div>+ /riscv_vhdl/trunk/debugger/msvc13/arm7_plugin<br />+ /riscv_vhdl/trunk/debugger/msvc13/arm7_plugin/arm7_plugin.vcxproj<br />+ /riscv_vhdl/trunk/debugger/msvc13/arm7_plugin/arm7_plugin.vcxproj.filters<br />+ /riscv_vhdl/trunk/debugger/msvc13/arm7_plugin/arm7_plugin.vcxproj.user<br />+ /riscv_vhdl/trunk/debugger/msvc13/arm7_plugin/exportmap.def<br />+ /riscv_vhdl/trunk/debugger/scripts<br />+ /riscv_vhdl/trunk/debugger/scripts/autotest1.py<br />+ /riscv_vhdl/trunk/debugger/scripts/rpc<br />+ /riscv_vhdl/trunk/debugger/scripts/rpc/client.py<br />+ /riscv_vhdl/trunk/debugger/scripts/rpc/events.py<br />+ /riscv_vhdl/trunk/debugger/scripts/rpc/safe.py<br />+ /riscv_vhdl/trunk/debugger/scripts/rpc/__init__.py<br />+ /riscv_vhdl/trunk/debugger/src/common/coreservices/icpuarm.h<br />+ /riscv_vhdl/trunk/debugger/src/common/coreservices/icpufunctional.h<br />+ /riscv_vhdl/trunk/debugger/src/common/coreservices/icpugen.h<br />+ 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/riscv_vhdl/trunk/rtl/work<br />+ /riscv_vhdl/trunk/rtl/work/config_common.vhd<br />+ /riscv_vhdl/trunk/rtl/work/riscv_soc.vhd<br />+ /riscv_vhdl/trunk/rtl/work/riscv_soc_gnss.vhd<br />+ /riscv_vhdl/trunk/rtl/work/tb<br />+ /riscv_vhdl/trunk/rtl/work/tb/jtag_sim.vhd<br />+ /riscv_vhdl/trunk/rtl/work/tb/patterns<br />+ /riscv_vhdl/trunk/rtl/work/tb/riscv_soc_tb.vhd<br />+ /riscv_vhdl/trunk/rtl/work/tb/tap_uart_tb.vhd<br />+ /riscv_vhdl/trunk/rtl/work/tb/uart_sim.vhd<br />
sergeykhbr
Sat, 17 Nov 2018 09:45:59 +0100
https://opencores.org/websvn//websvn/revision?repname=riscv_vhdl&path=%2Friscv_vhdl%2Ftrunk%2Fdebugger%2Fsrc%2Flibdbg64g%2Fservices%2Fremote%2F&rev=5
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