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https://opencores.org/websvn//websvn/listing?repname=socgen&path=%2Fsocgen%2Ftrunk%2Fdoc%2Ftemplate%2Ftemplate.html&
Thu, 25 Jun 2026 09:47:40 +0100
FeedCreator 1.7.2
-
added Nexys2 support
expanded docs
created tools directory
https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Fdoc%2Ftemplate%2F&rev=20
<div><strong>Rev 20 - jt_eaton</strong> (191 file(s) modified)</div><div>added Nexys2 support<br />
expanded docs<br />
created tools directory</div>~ /socgen/trunk/bench/verilog/TestBench<br />- /socgen/trunk/bin<br />+ /socgen/trunk/doc/src/drawing/sch/data_fig1.sch<br />+ /socgen/trunk/doc/src/drawing/sch/doc_fig1.sch<br />+ /socgen/trunk/doc/src/guides/guide_database.html<br />+ /socgen/trunk/doc/src/guides/guide_documentation.html<br />~ /socgen/trunk/doc/src/guides/guide_names.html<br />+ /socgen/trunk/doc/src/png<br />+ /socgen/trunk/doc/src/png/data_fig1.png<br />+ /socgen/trunk/doc/src/png/doc_fig1.png<br />+ /socgen/trunk/doc/src/png/naming_guide_1.png<br />~ /socgen/trunk/doc/src/prj_description.html<br />~ /socgen/trunk/doc/template/template.html<br />- /socgen/trunk/geda<br />+ /socgen/trunk/lib/cde_dft<br />+ /socgen/trunk/lib/cde_dft/cde_asyncdisable.v<br />+ /socgen/trunk/lib/cde_dft/cde_clk_diff_testmux.v<br />+ /socgen/trunk/lib/cde_dft/cde_clk_gater.v<br />+ /socgen/trunk/lib/cde_dft/cde_clk_testmux.v<br />+ /socgen/trunk/lib/cde_dft/cde_reset.v<br />~ /socgen/trunk/lib/cde_divider/cde_divider.v<br />~ /socgen/trunk/lib/cde_prescale/cde_prescale.v<br />~ /socgen/trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v<br />+ /socgen/trunk/lib/doc/drawing/cde_asyncdisable.png<br />+ /socgen/trunk/lib/doc/drawing/sch/cde_asyncdisable.sch<br />~ /socgen/trunk/lib/doc/drawing/sym/cde_asyncdisable.sym<br />~ /socgen/trunk/lib/doc/drawing/sym/cde_serial_rcvr.sym<br />+ /socgen/trunk/lib/doc/html/blocks.html<br />+ /socgen/trunk/lib/doc/html/cde_asyncdisable.html<br />+ /socgen/trunk/lib/doc/html/cde_clk_diff_testmux.html<br />+ /socgen/trunk/lib/doc/html/cde_clk_gater.html<br />+ /socgen/trunk/lib/doc/html/cde_clk_testmux.html<br />+ /socgen/trunk/lib/doc/html/cde_dft.html<br />~ /socgen/trunk/lib/doc/html/cde_divider.html<br />~ /socgen/trunk/lib/doc/html/cde_pad_se_dig.html<br />+ /socgen/trunk/lib/doc/html/cde_reset.html<br />~ /socgen/trunk/lib/doc/html/cde_serial_rcvr.html<br />~ /socgen/trunk/lib/doc/html/cde_serial_xmit.html<br />~ /socgen/trunk/lib/doc/html/cde_sram.html<br />~ /socgen/trunk/lib/doc/html/cde_sync.html<br />~ /socgen/trunk/lib/doc/html/cde_synchronizers.html<br />~ /socgen/trunk/lib/doc/html/cde_sync_with_hysteresis.html<br />~ /socgen/trunk/lib/doc/html/cde_sync_with_reset.html<br />+ /socgen/trunk/lib/doc/html/pads.html<br />+ /socgen/trunk/lib/doc/html/srams.html<br />~ /socgen/trunk/lib/doc/index.html<br />~ /socgen/trunk/lib/doc/png/cde_asyncdisable.png<br />~ /socgen/trunk/lib/doc/png/cde_serial_rcvr.png<br />~ /socgen/trunk/Makefile<br />~ /socgen/trunk/projects/logic/ip/io_module/rtl/verilog/io_module_ps2.v<br />~ /socgen/trunk/projects/logic/ip/io_module/sim/run/default/dut<br />~ /socgen/trunk/projects/logic/ip/io_module/sim/run/default/filelist<br />~ /socgen/trunk/projects/logic/ip/io_module/sim/run/default/liblist<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface.v<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/rtl/verilog/ps2_interface_fsm.v<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/dut<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/liblist<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/sav.sav<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/bin<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/bin/Makefile<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/copyright.v<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing/filelist<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing/sch<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing/sch/serial_xmit.sch<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing/sym<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/geda/drawing/sym/serial_xmit.sym<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/html<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/html/serial_xmit.html<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/index.html<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/png<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/png/serial_xmit.png<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/doc/timing<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants/serial_rcvr<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl/variants/serial_rcvr/serial_rcvr_defines.v<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/rtl/verilog/serial_rcvr.v<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/bin<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/bin/Makefile<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/log<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/out<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/dmp_define<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/dut<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/filelist<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/liblist<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/modellist<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/TB.defs<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/sim/run/default/test_define<br />+ /socgen/trunk/projects/logic/ip/serial_rcvr/syn<br />~ /socgen/trunk/projects/logic/ip/uart/rtl/variants/uart/uart_defines.v<br />~ /socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart.v<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/filelist<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/liblist<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/test_define<br />+ /socgen/trunk/projects/pic_micro/children/logic/ip/serial_rcvr<br />+ /socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/gate_sims<br />+ /socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/gate_sims/par<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/filelist<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/liblist<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/gate_sims<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/gate_sims/par<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/bsdl<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/bsdl/xc3s1200e_fg320_1532.bsd<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/core.v<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/debug<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/debug/fpga_load<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/debug/impact_bat<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/def_file<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/filelist<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/gate_sims<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/gate_sims/par<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/Makefile<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/sim<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/sim/bin<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/sim/log<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/sim/out<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/sim/run<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/target<br />+ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Nexys2_mouse_mrisc/target/Nexys2<br />+ /socgen/trunk/targets/Nexys2<br />+ /socgen/trunk/targets/Nexys2/bsdl<br />+ /socgen/trunk/targets/Nexys2/bsdl/xc3s1200e_fg320_1532.bsd<br />+ /socgen/trunk/targets/Nexys2/bsdl/xcf04s_vo20.bsd<br />+ /socgen/trunk/targets/Nexys2/cclk.ut<br />+ /socgen/trunk/targets/Nexys2/jtag.ut<br />+ /socgen/trunk/targets/Nexys2/lib<br />+ /socgen/trunk/targets/Nexys2/lib/syn<br />+ /socgen/trunk/targets/Nexys2/lib/syn/cde_clock_sys<br />+ /socgen/trunk/targets/Nexys2/lib/syn/cde_clock_sys/cde_clock_sys.v<br />+ /socgen/trunk/targets/Nexys2/lib/syn/cde_jtag<br />+ /socgen/trunk/targets/Nexys2/lib/syn/cde_jtag/cde_jtag.v<br />+ /socgen/trunk/targets/Nexys2/lib/syn/cde_jtag/cde_jtag_rpc_reg.v<br />+ /socgen/trunk/targets/Nexys2/Makefile.brd<br />+ /socgen/trunk/targets/Nexys2/Nexys2_1200General.ucf<br />+ /socgen/trunk/targets/Nexys2/Pad_Ring.ucf<br />+ /socgen/trunk/targets/Nexys2/Pad_Ring.v<br />+ /socgen/trunk/tools<br />+ /socgen/trunk/tools/bin<br />+ /socgen/trunk/tools/bin/build_cmp<br />+ /socgen/trunk/tools/bin/hex2abs<br />+ /socgen/trunk/tools/bin/hex2abs12<br />+ /socgen/trunk/tools/bin/hex2abs16<br />+ /socgen/trunk/tools/bin/hex2abs_split<br />+ /socgen/trunk/tools/bin/Makefile<br />+ /socgen/trunk/tools/bin/Makefile.root<br />+ /socgen/trunk/tools/bin/Makefile.root.x10<br />+ /socgen/trunk/tools/bin/Makefile.root.x11<br />+ /socgen/trunk/tools/bin/ver2gedasch<br />+ /socgen/trunk/tools/bin/ver2gedasym<br />+ /socgen/trunk/tools/geda<br />+ /socgen/trunk/tools/geda/dot_gEDA<br />+ /socgen/trunk/tools/geda/dot_gEDA/gafrc<br />+ /socgen/trunk/tools/geda/dot_gEDA/gschemrc<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_320x240.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_640x480.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_800x600.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_1200x768.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_1280x960.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_1600x1200.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/frames/frame_3200x2400.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/pads<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/pads/in_pad.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/pads/io_pad.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/pads/out_pad.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/pads/tri_pad.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/in_port.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/in_port_v.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/io_port.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/io_port_v.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/out_port.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/ports/out_port_v.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/regs<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/regs/reg.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/regs/reg_rst.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/regs/veg.sym<br />+ /socgen/trunk/tools/geda/dot_gEDA/sym/regs/veg_rst.sym<br />+ /socgen/trunk/tools/geda/Makefile<br />+ /socgen/trunk/tools/geda/README.txt<br />
jt_eaton
Wed, 05 May 2010 05:16:30 +0100
https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Fdoc%2Ftemplate%2F&rev=20
-
added serial_xmit module
updated and added docs
https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Fdoc%2Ftemplate%2F&rev=19
<div><strong>Rev 19 - jt_eaton</strong> (151 file(s) modified)</div><div>added serial_xmit module<br />
updated and added docs</div>+ /socgen/trunk/doc/pdf<br />+ /socgen/trunk/doc/pdf/guide_names.pdf<br />+ /socgen/trunk/doc/src/drawing<br />+ /socgen/trunk/doc/src/drawing/sch<br />+ /socgen/trunk/doc/src/drawing/sch/naming_guide_1.png<br />+ /socgen/trunk/doc/src/drawing/sch/naming_guide_1.sch<br />+ /socgen/trunk/doc/src/drawing/sym<br />+ /socgen/trunk/doc/src/guides<br />+ /socgen/trunk/doc/src/guides/guide_names.html<br />+ /socgen/trunk/doc/src/guides/reset_sys_design.html<br />+ /socgen/trunk/doc/template<br />+ /socgen/trunk/doc/template/template.html<br />~ /socgen/trunk/geda/dot_gEDA/gschemrc<br />+ /socgen/trunk/lib/cde_divider<br />+ /socgen/trunk/lib/cde_divider/cde_divider.v<br />+ /socgen/trunk/lib/cde_prescale<br />+ /socgen/trunk/lib/cde_prescale/cde_prescale.v<br />+ /socgen/trunk/lib/cde_serial_rcvr<br />+ /socgen/trunk/lib/cde_serial_rcvr/cde_serial_rcvr.v<br />+ /socgen/trunk/lib/cde_serial_xmit<br />+ /socgen/trunk/lib/cde_serial_xmit/cde_serial_xmit.v<br />~ /socgen/trunk/lib/cde_sram/cde_sram.v<br />- /socgen/trunk/lib/cde_sync<br />+ /socgen/trunk/lib/cde_synchronizers<br />+ /socgen/trunk/lib/cde_synchronizers/cde_sync.v<br />+ /socgen/trunk/lib/cde_synchronizers/cde_sync_with_hysteresis.v<br />+ /socgen/trunk/lib/cde_synchronizers/cde_sync_with_reset.v<br />+ /socgen/trunk/lib/doc<br />+ /socgen/trunk/lib/doc/drawing<br />+ /socgen/trunk/lib/doc/drawing/sch<br />+ /socgen/trunk/lib/doc/drawing/sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_asyncdisable.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_clk_diff_testmux.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_clk_gater.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_clk_testmux.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_clock_sys.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_clock_sys_mult.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_divider.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_jtag.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_jtag_rpc_reg.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_lifo.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_pad_se_dig.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_prescale.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_reset.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_serial_rcvr.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_serial_xmit.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_sram.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_sync.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_sync_with_hysteresis.sym<br />+ /socgen/trunk/lib/doc/drawing/sym/cde_sync_with_reset.sym<br />+ /socgen/trunk/lib/doc/html<br />+ /socgen/trunk/lib/doc/html/cde_divider.html<br />+ /socgen/trunk/lib/doc/html/cde_pads.html<br />+ /socgen/trunk/lib/doc/html/cde_pad_se_dig.html<br />+ /socgen/trunk/lib/doc/html/cde_prescale.html<br />+ /socgen/trunk/lib/doc/html/cde_serial_rcvr.html<br />+ /socgen/trunk/lib/doc/html/cde_serial_xmit.html<br />+ /socgen/trunk/lib/doc/html/cde_sram.html<br />+ /socgen/trunk/lib/doc/html/cde_sync.html<br />+ /socgen/trunk/lib/doc/html/cde_synchronizers.html<br />+ /socgen/trunk/lib/doc/html/cde_sync_with_hysteresis.html<br />+ /socgen/trunk/lib/doc/html/cde_sync_with_reset.html<br />+ /socgen/trunk/lib/doc/index.html<br />+ /socgen/trunk/lib/doc/pdf<br />+ /socgen/trunk/lib/doc/pdf/cde_sram.pdf<br />+ /socgen/trunk/lib/doc/png<br />+ /socgen/trunk/lib/doc/png/cde_asyncdisable.png<br />+ /socgen/trunk/lib/doc/png/cde_clk_diff_testmux.png<br />+ /socgen/trunk/lib/doc/png/cde_clk_gater.png<br />+ /socgen/trunk/lib/doc/png/cde_clk_testmux.png<br />+ /socgen/trunk/lib/doc/png/cde_clock_sys.png<br />+ /socgen/trunk/lib/doc/png/cde_divider.png<br />+ /socgen/trunk/lib/doc/png/cde_jtag.png<br />+ /socgen/trunk/lib/doc/png/cde_jtag_rpc_reg.png<br />+ /socgen/trunk/lib/doc/png/cde_lifo.png<br />+ /socgen/trunk/lib/doc/png/cde_pad_se_dig.png<br />+ /socgen/trunk/lib/doc/png/cde_prescale.png<br />+ /socgen/trunk/lib/doc/png/cde_reset.png<br />+ /socgen/trunk/lib/doc/png/cde_serial_rcvr.png<br />+ /socgen/trunk/lib/doc/png/cde_serial_xmit.png<br />+ /socgen/trunk/lib/doc/png/cde_sram.png<br />+ /socgen/trunk/lib/doc/png/cde_sync.png<br />+ /socgen/trunk/lib/doc/png/cde_sync_with_hysteresis.png<br />+ /socgen/trunk/lib/doc/png/cde_sync_with_reset.png<br />~ /socgen/trunk/Makefile<br />~ /socgen/trunk/projects/logic/ip/io_module/doc/geda/drawing/filelist<br />~ /socgen/trunk/projects/logic/ip/io_module/sim/run/default/filelist<br />~ /socgen/trunk/projects/logic/ip/io_module/sim/run/default/liblist<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/doc/geda/drawing/filelist<br />~ /socgen/trunk/projects/logic/ip/ps2_interface/sim/run/default/liblist<br />+ /socgen/trunk/projects/logic/ip/serial_xmit<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/bin<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/bin/Makefile<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/copyright.v<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/filelist<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sch<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sch/serial_xmit.sch<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sym<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/geda/drawing/sym/serial_xmit.sym<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/html<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/html/serial_xmit.html<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/index.html<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/png<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/png/serial_xmit.png<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/doc/timing<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl/variants<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl/variants/serial_xmit<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl/variants/serial_xmit/serial_xmit_defines.v<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl/verilog<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/rtl/verilog/serial_xmit.v<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/bin<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/bin/Makefile<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/log<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/out<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/dmp_define<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/dut<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/filelist<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/liblist<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/modellist<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/TB.defs<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/sim/run/default/test_define<br />+ /socgen/trunk/projects/logic/ip/serial_xmit/syn<br />~ /socgen/trunk/projects/logic/ip/uart/rtl/variants/uart/uart_defines.v<br />~ /socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart.v<br />- /socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart_baudgen.v<br />- /socgen/trunk/projects/logic/ip/uart/rtl/verilog/uart_xmit.v<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/dut<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/filelist<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/liblist<br />~ /socgen/trunk/projects/logic/ip/uart/sim/run/default/test_define<br />+ /socgen/trunk/projects/pic_micro/children/logic/ip/serial_xmit<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/rtl/verilog/mrisc_register_file.v<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/loop/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf1/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf2/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/rf3/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity1/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/sim/run/sanity2/dut<br />~ /socgen/trunk/projects/pic_micro/ip/mrisc/syn/Basys_loop/core.v<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/doc/geda/drawing/filelist<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/rtl/verilog/soc_mouse.v<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/filelist<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/sim/run/mouse_mrisc/liblist<br />~ /socgen/trunk/projects/pic_micro/ip/soc_mouse/syn/Basys_mouse_mrisc/filelist<br />
jt_eaton
Tue, 27 Apr 2010 23:11:16 +0100
https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Fdoc%2Ftemplate%2F&rev=19
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