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/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu1_i.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo_i.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp_i.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jtag_i.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jfifo.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jsp.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_i.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_bfm.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu0_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu0_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu0_lint.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu0_tb.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu1_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu1_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu1_lint.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_cpu1_tb.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_jfifo_bfm.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_jfifo_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_jfifo_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_jfifo_lint.xml ~ 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/socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_jfifo_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_jfifo_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_jsp_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_jsp_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu0_lint.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu2_jsp_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu2_jsp_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_cpu2_jsp_lint.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_duth.design.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_lint.xml ~ /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_wb_tb.xml + /socgen/trunk/Projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/x - /socgen/trunk/Projects/opencores.org/fpgas/bin - /socgen/trunk/Projects/opencores.org/fpgas/doc/Geda + /socgen/trunk/Projects/opencores.org/fpgas/doc/html/iceskate_default.html + /socgen/trunk/Projects/opencores.org/fpgas/doc/html/logipi_T6502_default.html ~ /socgen/trunk/Projects/opencores.org/fpgas/doc/html/Nexys2_T6502_default.html + /socgen/trunk/Projects/opencores.org/fpgas/doc/png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/iceskate_default_sch.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/iceskate_default_sym.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/logipi_T6502_default_sch.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/logipi_T6502_default_sym.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/Nexys2_T6502_default_sch.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/png/Nexys2_T6502_default_sym.png + /socgen/trunk/Projects/opencores.org/fpgas/doc/sch + /socgen/trunk/Projects/opencores.org/fpgas/doc/sch/iceskate_default.sch + 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/socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/chips/xml/Nexys2_T6502_chip.xml ~ /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/ledtest.svf + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/olimex_nexys2.cfg + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/Readme.txt + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/target + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/target/bsdl + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/target/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/target/bsdl/xcf04s_vo20.bsd + /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/target/cclk.ut + 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/socgen/trunk/Projects/opencores.org/io/doc/html/io_ext_mem_interface_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_gpio_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_module_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_module_gpio.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_module_mouse.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_pic_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_ps2_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_ps2_mouse.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_timer_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_uart_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_uart_rx.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_uart_rxtx.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_uart_tx.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_utimer_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_vga_def.html ~ /socgen/trunk/Projects/opencores.org/io/doc/html/io_vic_def.html + /socgen/trunk/Projects/opencores.org/io/doc/png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_ext_mem_interface_def_sch.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_ext_mem_interface_def_sym.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_gpio_def_sch.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_gpio_def_sym.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_def_sch.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_def_sym.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_gpio_sch.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_gpio_sym.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_mouse_sch.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_module_mouse_sym.png + /socgen/trunk/Projects/opencores.org/io/doc/png/io_pic_def_sch.png + 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/socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/componentCfg.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_big.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_lit.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_big.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_lit.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.xml - /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/bin ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bfm.design.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_dut.params.xml ~ /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_duth.design.xml ~ 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/socgen/trunk/tools/geda/Makefile + /socgen/trunk/tools/geda/mk_sch_png + /socgen/trunk/tools/geda/mk_sym_png + /socgen/trunk/tools/geda/README.txt - /socgen/trunk/tools/icarus - /socgen/trunk/tools/install + /socgen/trunk/tools/ip-xact + /socgen/trunk/tools/ip-xact/1685-2009 + /socgen/trunk/tools/ip-xact/1685-2009/abstractionDefinition.xsd + /socgen/trunk/tools/ip-xact/1685-2009/abstractor.xsd + /socgen/trunk/tools/ip-xact/1685-2009/autoConfigure.xsd + /socgen/trunk/tools/ip-xact/1685-2009/busDefinition.xsd + /socgen/trunk/tools/ip-xact/1685-2009/busInterface.xsd + /socgen/trunk/tools/ip-xact/1685-2009/commonStructures.xsd + /socgen/trunk/tools/ip-xact/1685-2009/component.xsd + /socgen/trunk/tools/ip-xact/1685-2009/configurable.xsd + /socgen/trunk/tools/ip-xact/1685-2009/constraints.xsd + /socgen/trunk/tools/ip-xact/1685-2009/design.xsd + /socgen/trunk/tools/ip-xact/1685-2009/designConfig.xsd + /socgen/trunk/tools/ip-xact/1685-2009/file.xsd + /socgen/trunk/tools/ip-xact/1685-2009/fileType.xsd + /socgen/trunk/tools/ip-xact/1685-2009/generator.xsd + /socgen/trunk/tools/ip-xact/1685-2009/identifier.xsd + /socgen/trunk/tools/ip-xact/1685-2009/index.xsd + /socgen/trunk/tools/ip-xact/1685-2009/map + /socgen/trunk/tools/ip-xact/1685-2009/memoryMap.xsd + /socgen/trunk/tools/ip-xact/1685-2009/model.xsd + /socgen/trunk/tools/ip-xact/1685-2009/port.xsd + /socgen/trunk/tools/ip-xact/1685-2009/signalDrivers.xsd + /socgen/trunk/tools/ip-xact/1685-2009/simpleTypes.xsd + /socgen/trunk/tools/ip-xact/1685-2009/subInstances.xsd + /socgen/trunk/tools/ip-xact/1685-2009/TGI + /socgen/trunk/tools/ip-xact/1685-2009/TGI/TGI.html + /socgen/trunk/tools/ip-xact/1685-2009/TGI/TGI.wsdl + /socgen/trunk/tools/ip-xact/1685-2014 + /socgen/trunk/tools/ip-xact/1685-2014/abstractionDefinition.xsd + /socgen/trunk/tools/ip-xact/1685-2014/abstractor.xsd + /socgen/trunk/tools/ip-xact/1685-2014/autoConfigure.xsd + /socgen/trunk/tools/ip-xact/1685-2014/busDefinition.xsd + /socgen/trunk/tools/ip-xact/1685-2014/busInterface.xsd + /socgen/trunk/tools/ip-xact/1685-2014/catalog.xsd + /socgen/trunk/tools/ip-xact/1685-2014/commonStructures.xsd + /socgen/trunk/tools/ip-xact/1685-2014/component.xsd + /socgen/trunk/tools/ip-xact/1685-2014/configurable.xsd + /socgen/trunk/tools/ip-xact/1685-2014/constraints.xsd + /socgen/trunk/tools/ip-xact/1685-2014/design.xsd + /socgen/trunk/tools/ip-xact/1685-2014/designConfig.xsd + /socgen/trunk/tools/ip-xact/1685-2014/file.xsd + /socgen/trunk/tools/ip-xact/1685-2014/fileType.xsd + /socgen/trunk/tools/ip-xact/1685-2014/generator.xsd + /socgen/trunk/tools/ip-xact/1685-2014/identifier.xsd + /socgen/trunk/tools/ip-xact/1685-2014/index.xsd + /socgen/trunk/tools/ip-xact/1685-2014/memoryMap.xsd + /socgen/trunk/tools/ip-xact/1685-2014/model.xsd + /socgen/trunk/tools/ip-xact/1685-2014/port.xsd + /socgen/trunk/tools/ip-xact/1685-2014/signalDrivers.xsd + /socgen/trunk/tools/ip-xact/1685-2014/simpleTypes.xsd + /socgen/trunk/tools/ip-xact/1685-2014/subInstances.xsd + /socgen/trunk/tools/ip-xact/1685-2014/xml.xsd + /socgen/trunk/tools/ip-xact/1685.1 + /socgen/trunk/tools/ip-xact/1685.1/autoConfigure.xsd + /socgen/trunk/tools/ip-xact/1685.1/commonStructures.xsd + /socgen/trunk/tools/ip-xact/1685.1/component.xsd + /socgen/trunk/tools/ip-xact/1685.1/configurable.xsd + /socgen/trunk/tools/ip-xact/1685.1/constraints.xsd + /socgen/trunk/tools/ip-xact/1685.1/design.xsd + /socgen/trunk/tools/ip-xact/1685.1/designConfig.xsd + /socgen/trunk/tools/ip-xact/1685.1/file.xsd + /socgen/trunk/tools/ip-xact/1685.1/fileType.xsd + /socgen/trunk/tools/ip-xact/1685.1/generator.xsd + /socgen/trunk/tools/ip-xact/1685.1/identifier.xsd + /socgen/trunk/tools/ip-xact/1685.1/index.xsd + /socgen/trunk/tools/ip-xact/1685.1/map + /socgen/trunk/tools/ip-xact/1685.1/model.xsd + /socgen/trunk/tools/ip-xact/1685.1/port.xsd + /socgen/trunk/tools/ip-xact/1685.1/signalDrivers.xsd + /socgen/trunk/tools/ip-xact/1685.1/simpleTypes.xsd + /socgen/trunk/tools/ip-xact/1685.1/subInstances.xsd + /socgen/trunk/tools/license/Boilerplate.txt + /socgen/trunk/tools/padring + /socgen/trunk/tools/padring/component_boilerplate + /socgen/trunk/tools/padring/create_padring + /socgen/trunk/tools/padring/create_padring.safe + /socgen/trunk/tools/padring/design_boilerplate ~ /socgen/trunk/tools/regtool/gen_registers ~ /socgen/trunk/tools/simulation/build_coverage ~ /socgen/trunk/tools/simulation/build_icarus_filelists + /socgen/trunk/tools/simulation/build_icarus_filelists.cand ~ /socgen/trunk/tools/simulation/build_lint_filelists ~ /socgen/trunk/tools/simulation/build_sim_master ~ /socgen/trunk/tools/simulation/build_verilator_filelists ~ /socgen/trunk/tools/simulation/run_coverage ~ /socgen/trunk/tools/simulation/run_icarus ~ /socgen/trunk/tools/simulation/run_lint ~ /socgen/trunk/tools/simulation/run_sims ~ /socgen/trunk/tools/simulation/run_verilator ~ /socgen/trunk/tools/synthesys/build_fpga_master + /socgen/trunk/tools/synthesys/run_ara ~ /socgen/trunk/tools/synthesys/run_ise + /socgen/trunk/tools/synthesys/targets/ip/iceskate + /socgen/trunk/tools/synthesys/targets/ip/iceskate/bsdl + /socgen/trunk/tools/synthesys/targets/ip/iceskate/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/tools/synthesys/targets/ip/iceskate/bsdl/xcf04s_vo20.bsd + /socgen/trunk/tools/synthesys/targets/ip/iceskate/cclk.ut + /socgen/trunk/tools/synthesys/targets/ip/iceskate/jtag.ut + /socgen/trunk/tools/synthesys/targets/ip/iceskate/padring.pcf + /socgen/trunk/tools/synthesys/targets/ip/iceskate/Pad_Ring.ucf + /socgen/trunk/tools/synthesys/targets/ip/logipi + /socgen/trunk/tools/synthesys/targets/ip/logipi/bsdl + /socgen/trunk/tools/synthesys/targets/ip/logipi/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/tools/synthesys/targets/ip/logipi/bsdl/xcf04s_vo20.bsd + /socgen/trunk/tools/synthesys/targets/ip/logipi/cclk.ut + /socgen/trunk/tools/synthesys/targets/ip/logipi/jtag.ut + /socgen/trunk/tools/synthesys/targets/ip/logipi/Pad_Ring.ucf + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151 + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/doc + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/doc/Spartan6 + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/doc/Spartan6/ds160.pdf + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/doc/Spartan6/ds162.pdf + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/doc/Spartan6/ug385.pdf + /socgen/trunk/tools/synthesys/targets/ip/logipi_r151/Pad_Ring.ucf ~ /socgen/trunk/tools/sys/build_elab_master ~ /socgen/trunk/tools/sys/build_generate ~ /socgen/trunk/tools/sys/build_hw_master ~ /socgen/trunk/tools/sys/build_sw_master ~ /socgen/trunk/tools/sys/gen_child_filelist ~ /socgen/trunk/tools/sys/gen_elab_child_filelist ~ /socgen/trunk/tools/sys/soc_link_child ~ /socgen/trunk/tools/sys/workspace ~ /socgen/trunk/tools/verilog/elab_config_verilog ~ /socgen/trunk/tools/verilog/elab_verilog - /socgen/trunk/tools/verilog/gen_auxiliary ~ /socgen/trunk/tools/verilog/gen_design ~ /socgen/trunk/tools/verilog/gen_elab_verilog ~ /socgen/trunk/tools/verilog/gen_elab_verilogLib ~ /socgen/trunk/tools/verilog/gen_instance_roots ~ /socgen/trunk/tools/verilog/gen_ports ~ /socgen/trunk/tools/verilog/gen_root ~ /socgen/trunk/tools/verilog/gen_signals ~ /socgen/trunk/tools/verilog/gen_tb ~ /socgen/trunk/tools/verilog/gen_testbench ~ /socgen/trunk/tools/verilog/gen_verilog ~ /socgen/trunk/tools/verilog/gen_verilogLib ~ /socgen/trunk/tools/verilog/gen_vhdl ~ /socgen/trunk/tools/verilog/read_elab ~ /socgen/trunk/tools/verilog/read_ports ~ /socgen/trunk/tools/verilog/trace_bus + /socgen/trunk/tools/yosys + /socgen/trunk/tools/yosys/cells.lib + /socgen/trunk/tools/yosys/T6502_def_tb.YOSYS + /socgen/trunk/tools/yosys/yosys.txt + /socgen/trunk/tools/yosys/yosys_manual.pdf + /socgen/trunk/tools/yosys/yosys_presentation.pdf ~ /socgen/trunk/tools/yp/clean + /socgen/trunk/tools/yp/Create_YP ~ /socgen/trunk/tools/yp/create_yp ~ /socgen/trunk/tools/yp/lib.pm ~ /socgen/trunk/tools/yp/read_db ~ /socgen/trunk/workspace.xml jt_eaton Tue, 01 Nov 2016 19:03:14 +0100 https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=135 Added elaboration databases and tools Added bus map creation tools https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=131 <div>Rev 131 - jt_eaton (3200 file(s) modified)</div><div>Added elaboration databases and tools Added bus map creation tools</div>+ /socgen/trunk/common + /socgen/trunk/common/opencores.org + /socgen/trunk/common/opencores.org/Busdefs + /socgen/trunk/common/opencores.org/Busdefs/clock + /socgen/trunk/common/opencores.org/Busdefs/clock/componentCfg.xml + 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/socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/verilog + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/verilog/tb.ext + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bfm.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_dut.params.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_dutg.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_lint.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_tb.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_dut.params.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_dutg.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_lint.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_tb.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_dut.params.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_dutg.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_lint.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_tb.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_dut.params.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_dutg.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_lint.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_tb.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_dut.params.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_dutg.design.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_lint.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_tb.xml + /socgen/trunk/Projects/opencores.org/wishbone/ip/wb_uart16550/syn + /socgen/trunk/Projects/opencores.org/wishbone/sw ~ /socgen/trunk/README ~ /socgen/trunk/test ~ /socgen/trunk/tools/bin/Makefile.root + /socgen/trunk/tools/busdefs + /socgen/trunk/tools/busdefs/check_busDefs + /socgen/trunk/tools/busdefs/create_busdefs + /socgen/trunk/tools/busdefs/gen_busdef ~ /socgen/trunk/tools/documentation/create_busdefs_doc ~ /socgen/trunk/tools/documentation/create_lib_doc + /socgen/trunk/tools/firmware + /socgen/trunk/tools/firmware/gen_crasm ~ /socgen/trunk/tools/fizzim/gen_fizzim + /socgen/trunk/tools/icarus + /socgen/trunk/tools/icarus/verilog-0.9.6.tar.gz ~ /socgen/trunk/tools/install/Ubuntu_14.10/Makefile ~ /socgen/trunk/tools/lint/sim_main2.cpp - /socgen/trunk/tools/regtool/gen_header ~ /socgen/trunk/tools/regtool/gen_registers ~ /socgen/trunk/tools/simulation/build_coverage ~ /socgen/trunk/tools/simulation/build_icarus_filelists ~ /socgen/trunk/tools/simulation/build_lint_filelists + /socgen/trunk/tools/simulation/build_sim_master ~ /socgen/trunk/tools/simulation/build_verilator_filelists ~ /socgen/trunk/tools/simulation/run_coverage + /socgen/trunk/tools/simulation/run_icarus ~ /socgen/trunk/tools/simulation/run_lint ~ /socgen/trunk/tools/simulation/run_sims + /socgen/trunk/tools/simulation/run_verilator ~ /socgen/trunk/tools/synthesys/build_fpgas + /socgen/trunk/tools/synthesys/build_fpga_master + /socgen/trunk/tools/synthesys/run_ise - /socgen/trunk/tools/sys/build_child_filelist + /socgen/trunk/tools/sys/build_elab_master ~ /socgen/trunk/tools/sys/build_generate ~ /socgen/trunk/tools/sys/build_hw + /socgen/trunk/tools/sys/build_hw_master + /socgen/trunk/tools/sys/build_sw + /socgen/trunk/tools/sys/build_sw_master + /socgen/trunk/tools/sys/elaborate_icarus + /socgen/trunk/tools/sys/elaborate_icarus_lib + /socgen/trunk/tools/sys/gen_child_filelist ~ /socgen/trunk/tools/sys/soc_link_child ~ /socgen/trunk/tools/sys/workspace + /socgen/trunk/tools/verilog/elab_verilog + /socgen/trunk/tools/verilog/gen_auxiliary + /socgen/trunk/tools/verilog/gen_ports + /socgen/trunk/tools/verilog/gen_signals ~ /socgen/trunk/tools/verilog/gen_verilog ~ /socgen/trunk/tools/verilog/gen_verilogLib + /socgen/trunk/tools/verilog/gen_vhdl + /socgen/trunk/tools/verilog/read_elab + /socgen/trunk/tools/verilog/read_ports + /socgen/trunk/tools/verilog/trace_bus - /socgen/trunk/tools/yp/Berkeley - /socgen/trunk/tools/yp/check_busDefs + /socgen/trunk/tools/yp/clean ~ /socgen/trunk/tools/yp/create_yp ~ /socgen/trunk/tools/yp/lib.pm + /socgen/trunk/tools/yp/read_db - /socgen/trunk/work + /socgen/trunk/workspace.xml jt_eaton Fri, 27 Mar 2015 19:30:33 +0100 https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=131 Dec 2014 major release trimmed out some IP replaced perl database with ... https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=130 <div>Rev 130 - jt_eaton (1264 file(s) modified)</div><div>Dec 2014 major release trimmed out some IP replaced perl database with ...</div>~ /socgen/trunk/Makefile - /socgen/trunk/make_doc + /socgen/trunk/profile + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/png + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/sch + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/src + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Geda/sym + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Heda + /socgen/trunk/projects/digilentinc.com/Nexys2/doc/Heda/busDef + /socgen/trunk/projects/digilentinc.com/Nexys2/Geda + /socgen/trunk/projects/digilentinc.com/Nexys2/Geda/png + /socgen/trunk/projects/digilentinc.com/Nexys2/Geda/sch + /socgen/trunk/projects/digilentinc.com/Nexys2/Geda/src + /socgen/trunk/projects/digilentinc.com/Nexys2/Geda/sym + /socgen/trunk/projects/digilentinc.com/Nexys2/Heda + /socgen/trunk/projects/digilentinc.com/Nexys2/Heda/busDef ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/xml/cde_clock_sys.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_core.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_jtag_padring.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/fpga/rtl/xml/Nexys2_fpga_padring.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/jtag/rtl/xml/cde_jtag_tap.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_in_dig.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_od_dig.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_out_dig.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_se_dig.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/pad/rtl/xml/cde_pad_tri_dig.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_be.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_def.xml ~ /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_dp.xml - /socgen/trunk/projects/github.com ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/componentCfg.xml + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu0.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_cpu1.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_jfifo.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_jsp.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jfifo.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu0_jsp.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/html/adv_dbg_if_wb_cpu2_jsp.html + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu0_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu0_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu1_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_cpu1_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jfifo_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jfifo_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jsp_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_jsp_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jfifo_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jfifo_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jsp_sch.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_jsp_sym.png + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/png/adv_dbg_if_wb_cpu0_sch.png + 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/socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_cpu1.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_jfifo.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_jsp.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0_jfifo.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu0_jsp.sym + /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/doc/Geda/sym/adv_dbg_if_wb_cpu2_jsp.sym ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu0.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu0_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu1.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_cpu1_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jfifo_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jsp_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_jtag_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jfifo.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu0_jsp.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_cpu2_jsp.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/rtl/xml/adv_dbg_if_wb_i.xml ~ /socgen/trunk/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/testbenches/xml/adv_dbg_if_bfm.design.xml - /socgen/trunk/projects/opencores.org/Busdefs/bin + /socgen/trunk/projects/opencores.org/Busdefs/clock + /socgen/trunk/projects/opencores.org/Busdefs/clock/componentCfg.xml + /socgen/trunk/projects/opencores.org/Busdefs/clock/doc + /socgen/trunk/projects/opencores.org/Busdefs/clock/doc/Heda + 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/socgen/trunk/projects/opencores.org/Busdefs/sw + /socgen/trunk/projects/opencores.org/Busdefs/uart + /socgen/trunk/projects/opencores.org/Busdefs/uart/componentCfg.xml + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/absDef + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/absDef/uart_rtl.txt + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/busDef + /socgen/trunk/projects/opencores.org/Busdefs/uart/doc/Heda/busDef/uart_def.txt + /socgen/trunk/projects/opencores.org/Busdefs/uart/xml + /socgen/trunk/projects/opencores.org/Busdefs/uart/xml/uart_def.busDefinition.xml + /socgen/trunk/projects/opencores.org/Busdefs/uart/xml/uart_def_rtl.abstractionDefinition.xml + /socgen/trunk/projects/opencores.org/Busdefs/vga + /socgen/trunk/projects/opencores.org/Busdefs/vga/componentCfg.xml + /socgen/trunk/projects/opencores.org/Busdefs/vga/doc + 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/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_sys.html + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/html/cde_clock_testmux.html + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_dll_sch.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_dll_sym.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_gater_sch.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_gater_sym.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_sys_sch.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_sys_sym.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_testmux_sch.png + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/png/cde_clock_testmux_sym.png + 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/socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/sym/cde_clock_gater.sym + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/sym/cde_clock_sys.sym + /socgen/trunk/projects/opencores.org/cde/ip/clock/doc/Geda/sym/cde_clock_testmux.sym ~ /socgen/trunk/projects/opencores.org/cde/ip/clock/rtl/xml/cde_clock_dll.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/clock/rtl/xml/cde_clock_gater.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/clock/rtl/xml/cde_clock_sys.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/clock/rtl/xml/cde_clock_testmux.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/divider/componentCfg.xml + /socgen/trunk/projects/opencores.org/cde/ip/divider/doc/Geda + /socgen/trunk/projects/opencores.org/cde/ip/divider/doc/Geda/html + /socgen/trunk/projects/opencores.org/cde/ip/divider/doc/Geda/html/cde_divider_def.html + /socgen/trunk/projects/opencores.org/cde/ip/divider/doc/Geda/png + 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/socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/png + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/png/cde_fifo_def_sch.png + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/png/cde_fifo_def_sym.png + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/sch + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/sch/cde_fifo_def.sch + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/src + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/src/cde_fifo_def.v + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/sym + /socgen/trunk/projects/opencores.org/cde/ip/fifo/doc/Geda/sym/cde_fifo_def.sym ~ /socgen/trunk/projects/opencores.org/cde/ip/fifo/rtl/xml/cde_fifo_def.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/jtag/busDef/xml/jtag_rpc.busDefinition.xml + /socgen/trunk/projects/opencores.org/cde/ip/jtag/busDef/xml/jtag_rpc_classic_rtl.abstractionDefinition.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/jtag/busDef/xml/jtag_rpc_rtl.abstractionDefinition.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/jtag/componentCfg.xml + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_classic_rpc_in_reg.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_classic_rpc_reg.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_classic_sync.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_rpc_in_reg.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_rpc_reg.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_sync.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/html/cde_jtag_tap.html + /socgen/trunk/projects/opencores.org/cde/ip/jtag/doc/Geda/png + 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/socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/io_irq_2 - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/io_poll_2 - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/irq_2_test - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2 - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2 - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/xml/Nexys2_T6502_kim_2.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/xml/Nexys2_T6502_tim_2.xml - /socgen/trunk/projects/opencores.org/fpga_or1200 + /socgen/trunk/projects/opencores.org/io/doc/Geda + /socgen/trunk/projects/opencores.org/io/doc/Geda/html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_ext_mem_interface_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_gpio_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_module_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_module_gpio.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_module_mouse.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_pic_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_ps2_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_ps2_mouse.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_timer_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_uart_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_uart_rx.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_uart_rxtx.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_uart_tx.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_utimer_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_vga_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/html/io_vic_def.html + /socgen/trunk/projects/opencores.org/io/doc/Geda/png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_ext_mem_interface_def_sch.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_ext_mem_interface_def_sym.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_gpio_def_sch.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_gpio_def_sym.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_def_sch.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_def_sym.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_gpio_sch.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_gpio_sym.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_mouse_sch.png + /socgen/trunk/projects/opencores.org/io/doc/Geda/png/io_module_mouse_sym.png + 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/socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_ext_mem_interface_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_gpio_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_module_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_module_gpio.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_module_mouse.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_pic_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_ps2_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_ps2_mouse.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_timer_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_uart_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_uart_rx.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_uart_rxtx.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_uart_tx.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_utimer_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_vga_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/src/io_vic_def.v + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_ext_mem_interface_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_gpio_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_module_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_module_gpio.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_module_mouse.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_pic_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_ps2_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_ps2_mouse.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_timer_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_uart_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_uart_rx.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_uart_rxtx.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_uart_tx.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_utimer_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_vga_def.sym + /socgen/trunk/projects/opencores.org/io/doc/Geda/sym/io_vic_def.sym ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/io_ext_mem_interface_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/io_gpio_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/io_module_def.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/io_module_gpio.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/io_module_mouse.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/io_ps2_def.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/io_ps2_mouse.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_timer/ip-xact/io_timer_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/io_uart_def.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/io_uart_rx.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/io_uart_rxtx.designCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/io_uart_tx.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_utimer/ip-xact/io_utimer_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vga/ip-xact/io_vga_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vic/ip-xact/io_vic_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml + /socgen/trunk/projects/opencores.org/logic/doc/Geda + /socgen/trunk/projects/opencores.org/logic/doc/Geda/html + /socgen/trunk/projects/opencores.org/logic/doc/Geda/html/disp_io_def.html + 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/socgen/trunk/projects/opencores.org/logic/doc/Geda/src/serial_rcvr_fifo.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/uart_def.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/uart_rx.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/uart_rxtx.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/uart_tx.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/usb_epp_def.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/src/vga_char_ctrl_def.v + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym/disp_io_def.sym + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym/flash_memcontrl_def.sym + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym/micro_bus_byte.sym + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym/micro_bus_def.sym + /socgen/trunk/projects/opencores.org/logic/doc/Geda/sym/micro_bus_exp5.sym + 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/socgen/trunk/projects/opencores.org/logic/ip/disp_io/rtl/xml/disp_io_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/ip-xact/flash_memcontrl_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/flash_memcontrl/rtl/xml/flash_memcontrl_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/micro_bus_byte.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/micro_bus_def.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/micro_bus_exp5.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/micro_bus_exp6.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/ip-xact/micro_bus_exp9.designCfg.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_byte.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp5.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp6.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/micro_bus/rtl/xml/micro_bus_exp9.xml + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/PS_2_Mouse_Interfacing.html + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Keyboard_Interface.html + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol.html + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/fpdin1.JPG + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/fpindin.JPG + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/ps2.JPG + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/qscope.JPG + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/sdl.jpg + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/sdl1.jpg + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/spindin.JPG + /socgen/trunk/projects/opencores.org/logic/ip/ps2_interface/doc/ref/The_PS_2_Mouse_Keyboard_Protocol_files/spindin1.JPG + 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/socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/serial_rcvr/rtl/xml/serial_rcvr_fifo.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/uart_def.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/uart_rx.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/uart_rxtx.designCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/uart/ip-xact/uart_tx.designCfg.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rx.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_rxtx.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/uart/rtl/xml/uart_tx.xml - /socgen/trunk/projects/opencores.org/logic/ip/usb_epp/ip-xact/usb_epp_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/usb_epp/rtl/xml/usb_epp_def.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/ip-xact/vga_char_ctrl_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/logic/ip/vga_char_ctrl/rtl/xml/vga_char_ctrl_def.xml + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/html + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/html/core_def.html + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/html/cpu_def.html + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/html/T6502_ctrl.html + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/html/T6502_def.html + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/png + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/png/core_def_sch.png + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/png/core_def_sym.png + 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/socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/src/cpu_def.v + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/src/T6502_ctrl.v + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/src/T6502_def.v + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/sym + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/sym/core_def.sym + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/sym/cpu_def.sym + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/sym/T6502_ctrl.sym + /socgen/trunk/projects/opencores.org/Mos6502/doc/Geda/sym/T6502_def.sym + /socgen/trunk/projects/opencores.org/Mos6502/doc/Heda + /socgen/trunk/projects/opencores.org/Mos6502/doc/Heda/busDef ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/core/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/core/rtl/verilog/sequencer ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/core/rtl/verilog/top.body ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/core/rtl/verilog/top.sim ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/core/rtl/xml/core_def.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/ip-xact/cpu_def.designCfg.xml - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/alu - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/alu_logic - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/control - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/copyright.v - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/defines - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/inst_decode - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/sequencer - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/state_fsm - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/top.body - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/top.rtl - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/verilog/top.sim ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/xml/cpu_def.design.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/rtl/xml/cpu_def.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/icarus/inst_2_test/wave.sav ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/testbenches/verilog/top.rtl ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/testbenches/xml/cpu_bfm.design.xml - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/testbenches/xml/cpu_def_dut.design.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/testbenches/xml/cpu_def_dutg.design.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/testbenches/xml/cpu_def_tb.xml - /socgen/trunk/projects/opencores.org/Mos6502/ip/cpu/sim/verilator ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/ip-xact/T6502_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_ctrl.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/rtl/xml/T6502_def.xml ~ /socgen/trunk/projects/opencores.org/Mos6502/ip/T6502/sim/icarus/io_irq_2/wave.sav - /socgen/trunk/projects/opencores.org/or1k - /socgen/trunk/projects/opencores.org/Testbench/bfms/clock_gen/ip-xact/clock_gen_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/clock_gen/rtl/xml/clock_gen_def.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/io_probe/ip-xact/io_probe_def.designCfg.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/io_probe/ip-xact/io_probe_in.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_def.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/io_probe/rtl/xml/io_probe_in.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/jtag_model/ip-xact/jtag_model_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/jtag_model/rtl/xml/jtag_model_def.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/micro_bus16_model/ip-xact/micro_bus16_model_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/micro_bus16_model/rtl/xml/micro_bus16_model_def.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/micro_bus_model/ip-xact/micro_bus_model_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/micro_bus_model/rtl/xml/micro_bus_model_def.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/ip-xact/mt45w8mw12_def.designCfg.xml ~ /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/xml/mt45w8mw12_def.xml - /socgen/trunk/projects/opencores.org/Testbench/bfms/or1200_dbg_model/ip-xact/or1200_dbg_model_def.designCfg.xml ~ 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/socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.xml - /socgen/trunk/projects/opencores.org/xfer ~ /socgen/trunk/README ~ /socgen/trunk/test + /socgen/trunk/tools/bin/adv_dbg_start + /socgen/trunk/tools/bin/adv_jtag_bridge + /socgen/trunk/tools/bin/as65 + /socgen/trunk/tools/bin/g + /socgen/trunk/tools/bin/ip_report + /socgen/trunk/tools/bin/keywords ~ /socgen/trunk/tools/bin/Makefile.root + /socgen/trunk/tools/bin/make_doc + /socgen/trunk/tools/bin/mk_sch_png + /socgen/trunk/tools/bin/mk_sym_png + /socgen/trunk/tools/bin/p65 + /socgen/trunk/tools/bin/prog_usbblaster + /socgen/trunk/tools/bin/repeater + /socgen/trunk/tools/bin/soc_manager + /socgen/trunk/tools/bin/urjtag + /socgen/trunk/tools/documentation/create_busdefs_doc ~ /socgen/trunk/tools/documentation/create_lib_doc ~ /socgen/trunk/tools/fizzim/gen_fizzim - /socgen/trunk/tools/geda - /socgen/trunk/tools/install/Ubuntu_12.04 + /socgen/trunk/tools/install/Ubuntu_14.10 + /socgen/trunk/tools/install/Ubuntu_14.10/Makefile + /socgen/trunk/tools/install/Ubuntu_14.10/Readme.txt - /socgen/trunk/tools/Jtag_programmers - /socgen/trunk/tools/orbuild ~ /socgen/trunk/tools/regtool/gen_header ~ /socgen/trunk/tools/regtool/gen_registers ~ /socgen/trunk/tools/simulation/build_coverage ~ /socgen/trunk/tools/simulation/build_icarus_filelists ~ /socgen/trunk/tools/simulation/build_lint_filelists ~ /socgen/trunk/tools/simulation/build_verilator_filelists + /socgen/trunk/tools/simulation/doc + /socgen/trunk/tools/simulation/doc/gtkwave.odt + /socgen/trunk/tools/simulation/doc/gtkwave.pdf ~ /socgen/trunk/tools/simulation/run_coverage ~ /socgen/trunk/tools/simulation/run_lint ~ /socgen/trunk/tools/simulation/run_sims ~ /socgen/trunk/tools/synthesys/build_fpgas - /socgen/trunk/tools/synthesys/build_syn_filelists + /socgen/trunk/tools/synthesys/targets/doc + /socgen/trunk/tools/synthesys/targets/doc/Basys + /socgen/trunk/tools/synthesys/targets/doc/Basys/Basys_rm.pdf + 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/socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/ds312.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/spartan3e_hdl.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/spartan3e_scm.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/spartan3_hdl.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/spartan3_scm.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/ug112.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/ug331.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/ug332.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/xapp174.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/xapp200.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/Spartan/xapp462.pdf + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/unisim_comp.v + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/xilinx_internal_jtag.v + /socgen/trunk/tools/synthesys/targets/doc/Xilinx/X_DCM_SP.v ~ /socgen/trunk/tools/sys/build_child_filelist - /socgen/trunk/tools/sys/build_child_filelists ~ /socgen/trunk/tools/sys/build_generate ~ /socgen/trunk/tools/sys/build_hw ~ /socgen/trunk/tools/sys/soc_link_child ~ /socgen/trunk/tools/sys/workspace ~ /socgen/trunk/tools/verilog/gen_verilog ~ /socgen/trunk/tools/verilog/gen_verilogLib + /socgen/trunk/tools/yp/Berkeley + /socgen/trunk/tools/yp/check_busDefs - /socgen/trunk/tools/yp/create_hier_index ~ /socgen/trunk/tools/yp/create_yp - /socgen/trunk/tools/yp/hier_index.xml - /socgen/trunk/tools/yp/index.xml ~ /socgen/trunk/tools/yp/lib.pm jt_eaton Sun, 14 Dec 2014 02:16:50 +0100 https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=130 major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation ... https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=128 <div>Rev 128 - jt_eaton (1717 file(s) modified)</div><div>major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools</div>~ /socgen/trunk/doc/src/guides/reset_sys_design.html ~ /socgen/trunk/Makefile + /socgen/trunk/make_doc + /socgen/trunk/projects/digilentinc.com/Nexys2/doc - /socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_clock - /socgen/trunk/projects/digilentinc.com/Nexys2/ip/cde_jtag + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/bin + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/bin/Makefile + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/ip-xact + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/ip-xact/componentCfg.xml + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/verilog + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/clock/rtl/verilog/syn + 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/socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_be.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_def.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/lint/sram_dp.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_be.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_def.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/verilog/sram_dp.v + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_be.xml + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_def.xml + /socgen/trunk/projects/digilentinc.com/Nexys2/ip/sram/rtl/xml/sram_dp.xml - /socgen/trunk/projects/github.com/mor1kx + /socgen/trunk/projects/github.com/openrisc + /socgen/trunk/projects/github.com/openrisc/bin + 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/socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_xmit_dutg.design.xml + /socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/cde_serial_xmit_lint.xml + /socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_rcvr_dut.params.xml + /socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_rcvr_dutg.design.xml + /socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_xmit_dut.params.xml + /socgen/trunk/projects/opencores.org/cde/ip/serial/sim/testbenches/xml/serial_xmit_dutg.design.xml - /socgen/trunk/projects/opencores.org/cde/ip/sram/bin + /socgen/trunk/projects/opencores.org/cde/ip/sram/componentCfg.xml + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/gafrc + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/html + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/html/cde_sram_be.html + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/html/cde_sram_def.html + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/html/cde_sram_dp.html + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/html/component.html + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/mk_png + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/png + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/png/sram_timing.png + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/sch + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/sch/sram_timing.sch + /socgen/trunk/projects/opencores.org/cde/ip/sram/doc/sym - /socgen/trunk/projects/opencores.org/cde/ip/sram/ip-xact - /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sim + /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_be.v + /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_def.v + /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/sram_dp.v - /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/verilog/syn ~ /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_be.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_def.xml ~ /socgen/trunk/projects/opencores.org/cde/ip/sram/rtl/xml/sram_dp.xml - /socgen/trunk/projects/opencores.org/cde/ip/sram/sim + /socgen/trunk/projects/opencores.org/cde/ip/sync + /socgen/trunk/projects/opencores.org/cde/ip/sync/componentCfg.xml + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc/html + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc/html/cde_sync_def.html + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc/html/cde_sync_with_hysteresis.html + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc/html/cde_sync_with_reset.html + /socgen/trunk/projects/opencores.org/cde/ip/sync/doc/html/component.html + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/verilog + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/verilog/sync_def.v + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/verilog/sync_with_hysteresis.v + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/verilog/sync_with_reset.v + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/xml + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/xml/cde_sync_def.xml + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/xml/cde_sync_with_hysteresis.xml + /socgen/trunk/projects/opencores.org/cde/ip/sync/rtl/xml/cde_sync_with_reset.xml + /socgen/trunk/projects/opencores.org/cde/license + /socgen/trunk/projects/opencores.org/cde/license/LICENSE-2.0.txt + /socgen/trunk/projects/opencores.org/fpgas/doc + /socgen/trunk/projects/opencores.org/fpgas/doc/html + /socgen/trunk/projects/opencores.org/fpgas/doc/html/Nexys2_T6502_default.html - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/doc/html - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/doc/png - /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/doc/timing ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/verilog/top.gpio ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.design.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_core.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/rtl/xml/Nexys2_T6502_default.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/io_irq_2/test_define ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/io_irq_2/wave.sav ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/io_poll_2/test_define ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/irq_2_test/test_define ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/kim_2/test_define ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/icarus/tim_2/test_define ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/xml/Nexys2_T6502_default_dut.params.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/xml/Nexys2_T6502_default_lint.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/xml/Nexys2_T6502_default_tb.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/debug + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_irq_2/xml/Nexys2_T6502_io_irq_2.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/debug + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_io_poll_2/xml/Nexys2_T6502_io_poll_2.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/debug + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_irq_2_test/xml/Nexys2_T6502_irq_2_test.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_kim_2/xml/Nexys2_T6502_kim_2.xml ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/debug + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpgas/ip/Nexys2_T6502/syn/ise/Nexys2_T6502_tim_2/xml/Nexys2_T6502_tim_2.xml + /socgen/trunk/projects/opencores.org/fpga_or1200/doc + /socgen/trunk/projects/opencores.org/fpga_or1200/doc/html + /socgen/trunk/projects/opencores.org/fpga_or1200/doc/html/Nexys2_minsoc_default.html - /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/html - /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/png - /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/doc/timing ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.jabc ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/verilog/top.soc_or ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_core.design.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_core.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/rtl/xml/Nexys2_minsoc_default.xml + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_dbg + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_dbg/dmp_define + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_dbg/test_define + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_dbg/wave.sav ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/test_define ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/icarus/uart-nocache_emb/wave.sav ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_default_dut.params.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_default_lint.xml ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/sim/testbenches/xml/Nexys2_minsoc_default_tb.xml - /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/soc ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/bsdl/xc3s1200e_fg320_1532.bsd + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/bsdl/xcf04s_vo20.bsd + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/debug + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/debug/fpga_load + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/debug/impact_bat + /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/debug/ledtest.svf ~ /socgen/trunk/projects/opencores.org/fpga_or1200/ip/Nexys2_minsoc/syn/ise/Nexys2_minsoc_uart/xml/Nexys2_minsoc_uart.xml + /socgen/trunk/projects/opencores.org/io/doc + /socgen/trunk/projects/opencores.org/io/doc/html + /socgen/trunk/projects/opencores.org/io/doc/html/io_ext_mem_interface_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_gpio_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_module_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_module_gpio.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_module_mouse.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_pic_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_ps2_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_ps2_mouse.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_timer_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_uart_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_uart_rx.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_uart_rxtx.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_uart_tx.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_utimer_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_vga_def.html + /socgen/trunk/projects/opencores.org/io/doc/html/io_vic_def.html ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/rtl/xml/io_ext_mem_interface_def.xml - /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/verilog ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_ext_mem_interface/sim/testbenches/xml/io_ext_mem_interface_def_tb.xml - /socgen/trunk/projects/opencores.org/io/ip/io_gpio/doc/html - /socgen/trunk/projects/opencores.org/io/ip/io_gpio/doc/timing ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/rtl/xml/io_gpio_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/testbenches/xml/io_gpio_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/testbenches/xml/io_gpio_def_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_gpio/sim/testbenches/xml/io_gpio_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_gpio.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/rtl/xml/io_module_mouse.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/default/test_define + /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/default_mouse + /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/default_mouse/dmp_define + /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/default_mouse/test_define + /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/default_mouse/wave.sav ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/gpio_default/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/mouse_mouse/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/icarus/mouse_mouse/wave.sav ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/verilog/top.ext ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/verilog/top.ext.gpio ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/verilog/top.ext.mouse ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_def_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_gpio_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_gpio_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_mouse_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_mouse_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_module/sim/testbenches/xml/io_module_mouse_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/rtl/xml/io_pic_def.xml - /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/testbenches/verilog ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/testbenches/xml/io_pic_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/testbenches/xml/io_pic_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_pic/sim/testbenches/xml/io_pic_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/rtl/xml/io_ps2_mouse.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/default/wave.sav ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/icarus/mouse_default/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/verilog/tb.ver ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/xml/io_ps2_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/xml/io_ps2_def_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/xml/io_ps2_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_ps2/sim/testbenches/xml/io_ps2_mouse_tb.xml - /socgen/trunk/projects/opencores.org/io/ip/io_timer/doc/html - /socgen/trunk/projects/opencores.org/io/ip/io_timer/doc/timing ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/rtl/xml/io_timer_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/testbenches/verilog/top.ext ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/testbenches/xml/io_timer_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/testbenches/xml/io_timer_def_lint.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_timer/sim/testbenches/xml/io_timer_def_tb.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/doc/html - /socgen/trunk/projects/opencores.org/io/ip/io_uart/doc/timing ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/verilog/top.body ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_def.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rx.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_rxtx.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/rtl/xml/io_uart_tx.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/verilog ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_rxtx_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_rxtx_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_rx_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_rx_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_tx_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_uart/sim/testbenches/xml/io_uart_tx_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/rtl/xml/io_utimer_def.xml - /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/testbenches/verilog - /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/testbenches/xml/io_utimer_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/testbenches/xml/io_utimer_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_utimer/sim/testbenches/xml/io_utimer_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/rtl/xml/io_vga_def.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/testbenches/verilog - /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/testbenches/xml/io_vga_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/testbenches/xml/io_vga_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vga/sim/testbenches/xml/io_vga_def_tb.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/rtl/xml/io_vic_def.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/icarus - /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/testbenches/verilog - /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/testbenches/xml/io_vic_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/testbenches/xml/io_vic_def_lint.xml - /socgen/trunk/projects/opencores.org/io/ip/io_vic/sim/testbenches/xml/io_vic_def_tb.xml + /socgen/trunk/projects/opencores.org/logic/doc + /socgen/trunk/projects/opencores.org/logic/doc/html + /socgen/trunk/projects/opencores.org/logic/doc/html/disp_io_def.html + /socgen/trunk/projects/opencores.org/logic/doc/html/flash_memcontrl_def.html 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/socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/testbenches/xml/or1200_dbg_lint.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/testbenches/xml/or1200_dbg_tb.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/testbenches/xml/or1200_dbg_vtb.xml + /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/verilator + /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/verilator/or1200-basic + /socgen/trunk/projects/opencores.org/or1k/ip/or1200/sim/verilator/or1200-basic/test_define - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_data.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cache/rtl/xml/or1200_cache_inst.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/verilog/copyright.v ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_alu.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_boot.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_cfgr.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_ctrl.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_dbg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_du.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_except.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_freeze.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_genpc.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_if.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_lsu.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_operandmuxes.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_rf.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_sprs.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_spr_mux.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_cpu/rtl/xml/or1200_cpu_wbmux.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_fpu/rtl/xml/or1200_fpu_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_data.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mmu/rtl/xml/or1200_mmu_inst.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_mult_mac/rtl/xml/or1200_mult_mac_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pic/rtl/xml/or1200_pic_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_pm/rtl/xml/or1200_pm_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_qmem/rtl/xml/or1200_qmem_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_sb/rtl/xml/or1200_sb_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_tt/rtl/xml/or1200_tt_def.xml - /socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/doc ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/or1k/ip/or1200_wb_biu/rtl/xml/or1200_wb_biu_def.xml + /socgen/trunk/projects/opencores.org/Testbench/bfms + /socgen/trunk/projects/opencores.org/Testbench/bfms/clock_gen + /socgen/trunk/projects/opencores.org/Testbench/bfms/clock_gen/bin + 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/socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12 + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/bin + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/bin/Makefile + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/ip-xact + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/ip-xact/componentCfg.xml + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/ip-xact/mt45w8mw12_def.designCfg.xml + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/copyright.v + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.sim + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/verilog/top.syn + /socgen/trunk/projects/opencores.org/Testbench/bfms/mt45w8mw12/rtl/xml + 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/socgen/trunk/projects/opencores.org/Testbench/doc/html/mt45w8mw12_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/html/or1200_dbg_model_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/html/ps2_host_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/html/ps2_model_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/html/uart_host_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/html/uart_model_def.html + /socgen/trunk/projects/opencores.org/Testbench/doc/pdf + /socgen/trunk/projects/opencores.org/Testbench/doc/pdf/Testbench.pdf + /socgen/trunk/projects/opencores.org/Testbench/doc/src + /socgen/trunk/projects/opencores.org/Testbench/doc/src/geda + /socgen/trunk/projects/opencores.org/Testbench/doc/src/geda/sch + /socgen/trunk/projects/opencores.org/Testbench/doc/src/geda/sch/clock_gen_def.sch + /socgen/trunk/projects/opencores.org/Testbench/doc/src/geda/sch/io_probe_def.sch + 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/socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/ip-xact/componentCfg.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/rtl/verilog/minsoc_tc_def ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/rtl/xml/minsoc_tc_def.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/icarus/minsoc/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/testbenches/verilog/top.rtl ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/testbenches/xml/minsoc_tc_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/testbenches/xml/minsoc_tc_def_dut.params.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/minsoc_tc/sim/testbenches/xml/minsoc_tc_def_tb.xml - /socgen/trunk/projects/opencores.org/wishbone/ip/model/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/model/ip-xact/componentCfg.xml - /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/rtl/xml/wb_memory_def.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/sim/testbenches/xml/wb_memory_def_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_memory/sim/testbenches/xml/wb_memory_def_tb.xml - /socgen/trunk/projects/opencores.org/wishbone/ip/wb_model/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_model/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_model/rtl/xml/wb_model_master.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/rtl/xml/wb_sdr_ctrl_def.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/sim/testbenches/verilog/top.rtl ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/sim/testbenches/xml/wb_sdr_ctrl_def_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_sdr_ctrl/sim/testbenches/xml/wb_sdr_ctrl_def_tb.xml - /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_arb.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_def.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_exp.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/rtl/xml/wb_traffic_cop_front.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/minsoc/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/icarus/test1/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/verilog/top.rtl + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_arb_dut.params.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_arb_dutg.design.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_def_dutg.design.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_def_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_def_tb.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_exp_dut.params.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_exp_dutg.design.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_front_dut.params.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_traffic_cop/sim/testbenches/xml/wb_traffic_cop_front_dutg.design.xml - /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/doc ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/ip-xact/componentCfg.xml + /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart1 ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_big.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus16_lit.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_big.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_bus32_lit.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/rtl/xml/wb_uart16550_def.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_big_default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus16_lit_default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_big_default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/bus32_lit_default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/icarus/default/test_define ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_big_tb.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus16_lit_tb.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_big_tb.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_bus32_lit_tb.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_lint.xml ~ /socgen/trunk/projects/opencores.org/wishbone/ip/wb_uart16550/sim/testbenches/xml/wb_uart16550_def_tb.xml + /socgen/trunk/projects/opencores.org/xfer/doc + /socgen/trunk/projects/opencores.org/xfer/doc/html + /socgen/trunk/projects/opencores.org/xfer/doc/html/adv_dbg_if_wb.html + /socgen/trunk/projects/opencores.org/xfer/doc/html/adv_dbg_if_wb_cpu.html + /socgen/trunk/projects/opencores.org/xfer/doc/html/adv_dbg_if_wb_cpu2_jsp.html + /socgen/trunk/projects/opencores.org/xfer/doc/html/minsoc_def.html - /socgen/trunk/projects/opencores.org/xfer/ip/adv_dbg_if - /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/doc ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/ip-xact/componentCfg.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/verilog/top.rtl ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.design.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/rtl/xml/minsoc_def.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/basic/test_define ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/basic/wave.sav ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/uart1/test_define ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/icarus/uart2/test_define ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/testbenches/verilog/tb.ext ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/testbenches/xml/minsoc_bfm.design.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/testbenches/xml/minsoc_def_dutg.design.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/testbenches/xml/minsoc_def_lint.xml ~ /socgen/trunk/projects/opencores.org/xfer/ip/minsoc/sim/testbenches/xml/minsoc_def_tb.xml ~ /socgen/trunk/test ~ /socgen/trunk/tools/bin/Makefile.root + /socgen/trunk/tools/documentation + /socgen/trunk/tools/documentation/create_lib_doc + /socgen/trunk/tools/documentation/template.html + /socgen/trunk/tools/documentation/ver2gedasch + /socgen/trunk/tools/documentation/ver2gedasym ~ /socgen/trunk/tools/fizzim/gen_fizzim + /socgen/trunk/tools/geda/dot_gEDA/sym/regs/latch.sym + /socgen/trunk/tools/geda/g_rc.c + /socgen/trunk/tools/geda/mk_sch_png + /socgen/trunk/tools/geda/mk_sym_png ~ /socgen/trunk/tools/Jtag_programmers/debug/fpga_load ~ /socgen/trunk/tools/regtool/gen_header ~ /socgen/trunk/tools/regtool/gen_registers ~ /socgen/trunk/tools/simulation/build_coverage ~ /socgen/trunk/tools/simulation/build_icarus_filelists ~ /socgen/trunk/tools/simulation/build_lint_filelists ~ /socgen/trunk/tools/simulation/build_verilator_filelists ~ /socgen/trunk/tools/simulation/run_coverage ~ /socgen/trunk/tools/simulation/run_lint ~ /socgen/trunk/tools/simulation/run_sims ~ /socgen/trunk/tools/synthesys/build_fpgas + /socgen/trunk/tools/sys/build_child_filelist ~ /socgen/trunk/tools/sys/build_generate ~ /socgen/trunk/tools/sys/build_hw ~ /socgen/trunk/tools/sys/workspace ~ /socgen/trunk/tools/verilog/gen_verilog ~ /socgen/trunk/tools/verilog/gen_verilogLib ~ /socgen/trunk/tools/yp/hier_index.xml ~ /socgen/trunk/tools/yp/index.xml ~ /socgen/trunk/tools/yp/lib.pm jt_eaton Sat, 14 Sep 2013 20:11:45 +0100 https://opencores.org/websvn//websvn/revision?repname=socgen&path=%2Fsocgen%2Ftrunk%2Ftools%2Fdocumentation%2F&rev=128

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