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uart16550 WebSVN RSS feed - uart16550 https://opencores.org/websvn//websvn/listing?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2Fuart_defines.v& Mon, 18 May 2026 22:15:34 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=106 <div><strong>Rev 106 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />- /tags<br />- /trunk<br />+ /uart16550<br />+ /uart16550/branches<br />+ /uart16550/tags<br />+ /uart16550/trunk<br />+ /uart16550/web_uploads<br /> root Tue, 10 Mar 2009 10:08:42 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=106 adjusted comment + define https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=89 <div><strong>Rev 89 - dries</strong> (1 file(s) modified)</div><div>adjusted comment + define</div>~ /trunk/rtl/verilog/uart_defines.v<br /> dries Fri, 12 Sep 2003 07:26:58 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=89 This fixes errors in some cases when data is being ... https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=87 <div><strong>Rev 87 - gorban</strong> (3 file(s) modified)</div><div>This fixes errors in some cases when data is being ...</div>~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_regs.v<br />~ /trunk/rtl/verilog/uart_rfifo.v<br /> gorban Wed, 11 Jun 2003 16:37:47 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=87 Bug Fixes: * Possible loss of sync and bad reception ... https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=79 <div><strong>Rev 79 - gorban</strong> (10 file(s) modified)</div><div>Bug Fixes:<br /> * Possible loss of sync and bad reception ...</div>+ /trunk/rtl/verilog/raminfr.v<br />~ /trunk/rtl/verilog/uart_debug_if.v<br />~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_receiver.v<br />~ /trunk/rtl/verilog/uart_regs.v<br />+ /trunk/rtl/verilog/uart_rfifo.v<br />+ /trunk/rtl/verilog/uart_tfifo.v<br />~ /trunk/rtl/verilog/uart_top.v<br />~ /trunk/rtl/verilog/uart_transmitter.v<br />~ /trunk/rtl/verilog/uart_wb.v<br /> gorban Mon, 22 Jul 2002 23:02:23 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=79 Endian define added. Big Byte Endian is selected by default. https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=75 <div><strong>Rev 75 - mohor</strong> (2 file(s) modified)</div><div>Endian define added. Big Byte Endian is selected by default.</div>~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_wb.v<br /> mohor Tue, 19 Feb 2002 16:56:06 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=75 Scratch register define added. https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=53 <div><strong>Rev 53 - mohor</strong> (1 file(s) modified)</div><div>Scratch register define added.</div>~ /trunk/rtl/verilog/uart_defines.v<br /> mohor Tue, 11 Dec 2001 08:55:40 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=53 Updated specification documentation. Added full 32-bit data bus interface, now as ... https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=48 <div><strong>Rev 48 - gorban</strong> (11 file(s) modified)</div><div>Updated specification documentation.<br /> Added full 32-bit data bus interface, now as ...</div>~ /trunk/bench/verilog/uart_test.v<br />+ /trunk/bench/verilog/wb_mast.v<br />~ /trunk/doc/src/UART_spec.doc<br />~ /trunk/doc/UART_spec.pdf<br />~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_receiver.v<br />~ /trunk/rtl/verilog/uart_regs.v<br />~ /trunk/rtl/verilog/uart_top.v<br />~ /trunk/rtl/verilog/uart_transmitter.v<br />~ /trunk/rtl/verilog/uart_wb.v<br />~ /trunk/sim/rtl_sim/bin/sim.tcl<br /> gorban Mon, 03 Dec 2001 21:44:29 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=48 Lots of fixes: Break condition wasn't handled correctly at all. LSR bits ... https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=45 <div><strong>Rev 45 - gorban</strong> (4 file(s) modified)</div><div>Lots of fixes:<br /> Break condition wasn't handled correctly at all.<br /> LSR bits ...</div>~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_fifo.v<br />~ /trunk/rtl/verilog/uart_receiver.v<br />~ /trunk/rtl/verilog/uart_regs.v<br /> gorban Mon, 26 Nov 2001 21:38:54 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=45 Things connected to parity changed. Clock devider changed. https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 <div><strong>Rev 29 - mohor</strong> (8 file(s) modified)</div><div>Things connected to parity changed.<br /> Clock devider changed.</div>~ /trunk/rtl/verilog/timescale.v<br />~ /trunk/rtl/verilog/uart_defines.v<br />~ /trunk/rtl/verilog/uart_fifo.v<br />~ /trunk/rtl/verilog/uart_receiver.v<br />~ /trunk/rtl/verilog/uart_regs.v<br />~ /trunk/rtl/verilog/uart_top.v<br />~ /trunk/rtl/verilog/uart_transmitter.v<br />~ /trunk/rtl/verilog/uart_wb.v<br /> mohor Fri, 24 Aug 2001 21:01:12 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE ... https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=27 <div><strong>Rev 27 - mohor</strong> (18 file(s) modified)</div><div>Stop bit bug fixed.<br /> Parity bug fixed.<br /> WISHBONE read cycle bug fixed,<br /> OE ...</div>+ /trunk/rtl/verilog<br />+ /trunk/rtl/verilog-backup<br />+ /trunk/rtl/verilog-backup/timescale.v<br />+ /trunk/rtl/verilog-backup/uart_defines.v<br />+ /trunk/rtl/verilog-backup/uart_fifo.v<br />+ /trunk/rtl/verilog-backup/uart_receiver.v<br />+ /trunk/rtl/verilog-backup/uart_regs.v<br />+ /trunk/rtl/verilog-backup/uart_top.v<br />+ /trunk/rtl/verilog-backup/uart_transmitter.v<br />+ /trunk/rtl/verilog-backup/uart_wb.v<br />+ /trunk/rtl/verilog/timescale.v<br />+ /trunk/rtl/verilog/uart_defines.v<br />+ /trunk/rtl/verilog/uart_fifo.v<br />+ /trunk/rtl/verilog/uart_receiver.v<br />+ /trunk/rtl/verilog/uart_regs.v<br />+ /trunk/rtl/verilog/uart_top.v<br />+ /trunk/rtl/verilog/uart_transmitter.v<br />+ /trunk/rtl/verilog/uart_wb.v<br /> mohor Thu, 23 Aug 2001 16:05:05 +0100 https://opencores.org/websvn//websvn/revision?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2F&rev=27

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