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versatile_mem_ctrl WebSVN RSS feed - versatile_mem_ctrl https://opencores.org/websvn//websvn/listing?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2Ftb.v& Tue, 28 Apr 2026 18:02:17 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=80 <div><strong>Rev 80 - mikaeljf</strong> (11 file(s) modified)</div><div>...</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />~ /versatile_mem_ctrl/trunk/bench/wb1_ddr.fzm<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/egress_fifo.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/sdr_16.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ddr.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_wb.v<br />~ /versatile_mem_ctrl/trunk/sim/rtl_sim/bin/wave_ddr.do<br /> mikaeljf Tue, 08 Jun 2010 11:14:37 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=80 work for limited test case https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=35 <div><strong>Rev 35 - unneback</strong> (6 file(s) modified)</div><div>work for limited test case</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />~ /versatile_mem_ctrl/trunk/doc/src/versatile_mem_ctrl.odt<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_wb.v<br /> unneback Thu, 18 Mar 2010 14:44:51 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=35 work for limited test case, no cke inhibit for fifo ... https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=33 <div><strong>Rev 33 - unneback</strong> (10 file(s) modified)</div><div>work for limited test case, no cke inhibit for fifo ...</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />~ /versatile_mem_ctrl/trunk/bench/tb_defines.v<br />~ /versatile_mem_ctrl/trunk/doc/src/versatile_mem_ctrl.odt<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/delay.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/sdr_16_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_counter.xls<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_wb.v<br /> unneback Thu, 18 Mar 2010 12:10:40 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=33 Updated the testbench to match the new wishbone interface. https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=32 <div><strong>Rev 32 - mikaeljf</strong> (2 file(s) modified)</div><div>Updated the testbench to match the new wishbone interface.</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br /> mikaeljf Mon, 15 Mar 2010 08:16:00 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=32 Adapted the test bench to the new wishbone interface. https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=29 <div><strong>Rev 29 - mikaeljf</strong> (1 file(s) modified)</div><div>Adapted the test bench to the new wishbone interface.</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br /> mikaeljf Tue, 09 Mar 2010 14:57:47 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=29 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. ... https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=28 <div><strong>Rev 28 - mikaeljf</strong> (7 file(s) modified)</div><div>Fixed typos and updated the rtl Makefile and Altera-Modelsim script. ...</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/dff_sr.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_counter.xls<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />~ /versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_altera.tcl<br /> mikaeljf Tue, 09 Mar 2010 13:12:02 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=28 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also ... https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=15 <div><strong>Rev 15 - mikaeljf</strong> (28 file(s) modified)</div><div>Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also ...</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />~ /versatile_mem_ctrl/trunk/bench/tb_defines.v<br />~ /versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm<br />~ /versatile_mem_ctrl/trunk/bench/wb1_ddr.fzm<br />~ /versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/dcm_pll.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_ff.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/delay.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/pre_delay_counter_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />+ /versatile_mem_ctrl/trunk/sim<br />+ /versatile_mem_ctrl/trunk/sim/rtl_sim<br />+ /versatile_mem_ctrl/trunk/sim/rtl_sim/bin<br />+ /versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_altera.tcl<br />+ /versatile_mem_ctrl/trunk/sim/rtl_sim/bin/sim_xilinx.tcl<br />+ /versatile_mem_ctrl/trunk/sim/rtl_sim/run<br />+ /versatile_mem_ctrl/trunk/syn/altera<br />+ /versatile_mem_ctrl/trunk/syn/altera/bin<br />+ /versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.sdc<br />+ /versatile_mem_ctrl/trunk/syn/altera/bin/versatile_memory_controller.tcl<br />+ /versatile_mem_ctrl/trunk/syn/altera/run<br />+ /versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_memory_controller.ucf<br />- /versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_mem_ctrl.ucf<br /> mikaeljf Thu, 04 Feb 2010 14:21:43 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=15 Added external feedback of DDR SDRAM clock. https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=14 <div><strong>Rev 14 - mikaeljf</strong> (1 file(s) modified)</div><div>Added external feedback of DDR SDRAM clock.</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br /> mikaeljf Fri, 06 Nov 2009 11:55:01 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=14 Modified DDR FSM for read and write, added counters for ... https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=13 <div><strong>Rev 13 - mikaeljf</strong> (15 file(s) modified)</div><div>Modified DDR FSM for read and write, added counters for ...</div>~ /versatile_mem_ctrl/trunk/bench/tb.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/burst_length_counter_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/latency_counter_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/pre_delay_counter_defines.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/ref_delay_counter_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br />+ /versatile_mem_ctrl/trunk/syn<br />+ /versatile_mem_ctrl/trunk/syn/xilinx<br />+ /versatile_mem_ctrl/trunk/syn/xilinx/bin<br />+ /versatile_mem_ctrl/trunk/syn/xilinx/bin/versatile_mem_ctrl.ucf<br />+ /versatile_mem_ctrl/trunk/syn/xilinx/run<br /> mikaeljf Fri, 06 Nov 2009 09:11:58 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=13 Initial version with support for DDR https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=11 <div><strong>Rev 11 - mikaeljf</strong> (24 file(s) modified)</div><div>Initial version with support for DDR</div>+ /versatile_mem_ctrl/trunk/bench/ddr<br />+ /versatile_mem_ctrl/trunk/bench/ddr/ddr2.v<br />+ /versatile_mem_ctrl/trunk/bench/ddr/ddr2_mcp.v<br />+ /versatile_mem_ctrl/trunk/bench/ddr/ddr2_module.v<br />+ /versatile_mem_ctrl/trunk/bench/ddr/ddr2_parameters.vh<br />+ /versatile_mem_ctrl/trunk/bench/ddr/readme.txt<br />+ /versatile_mem_ctrl/trunk/bench/ddr/subtest.vh<br />+ /versatile_mem_ctrl/trunk/bench/ddr/tb.do<br />+ /versatile_mem_ctrl/trunk/bench/ddr/tb.v<br />~ /versatile_mem_ctrl/trunk/bench/Makefile<br />~ /versatile_mem_ctrl/trunk/bench/tb.v<br />+ /versatile_mem_ctrl/trunk/bench/tb_defines.v<br />+ /versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm<br />+ /versatile_mem_ctrl/trunk/bench/wb1_ddr.fzm<br />+ /versatile_mem_ctrl/trunk/bench/wb4_ddr.fzm<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/cke_delay_counter_defines.v<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16.fzm<br />+ /versatile_mem_ctrl/trunk/rtl/verilog/ddr_16_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/inc_adr.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/Makefile<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/sdr_16.fzm<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_defines.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_ip.v<br />~ /versatile_mem_ctrl/trunk/rtl/verilog/versatile_mem_ctrl_top.v<br /> mikaeljf Mon, 26 Oct 2009 20:41:33 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=11 testbench https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=9 <div><strong>Rev 9 - unneback</strong> (12 file(s) modified)</div><div>testbench</div>+ /versatile_mem_ctrl/trunk/bench<br />+ /versatile_mem_ctrl/trunk/bench/fizzim.pl<br />+ /versatile_mem_ctrl/trunk/bench/Makefile<br />+ /versatile_mem_ctrl/trunk/bench/mt48lc16m16a2.v<br />+ /versatile_mem_ctrl/trunk/bench/tb.v<br />+ /versatile_mem_ctrl/trunk/bench/transcript<br />+ /versatile_mem_ctrl/trunk/bench/wb0.fzm<br />+ /versatile_mem_ctrl/trunk/bench/wb0.v<br />+ /versatile_mem_ctrl/trunk/bench/wb1.fzm<br />+ /versatile_mem_ctrl/trunk/bench/wb1.v<br />+ /versatile_mem_ctrl/trunk/bench/wb4.fzm<br />+ /versatile_mem_ctrl/trunk/bench/wb4.v<br /> unneback Tue, 29 Sep 2009 12:35:24 +0100 https://opencores.org/websvn//websvn/revision?repname=versatile_mem_ctrl&path=%2Fversatile_mem_ctrl%2Ftrunk%2Fbench%2F&rev=9

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