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a-z80 WebSVN RSS feed - a-z80 https://opencores.org/websvn//websvn/listing?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F& Wed, 15 Jul 2020 01:17:16 +0100 FeedCreator 1.7.2 Documentation update https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=22 <div><strong>Rev 22 - gdevic</strong> (9 file(s) modified)</div><div>Documentation update</div>~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/docs/QuickStart.docx<br />~ /a-z80/trunk/docs/QuickStart.pdf<br />~ /a-z80/trunk/readme.txt<br />~ /a-z80/trunk/resources/process-pla.py<br />~ /a-z80/trunk/tools/readme.txt<br />~ /a-z80/trunk/tools/z80_pla_checker/readme.txt<br />~ /a-z80/trunk/tools/zmac/readme.txt<br /> gdevic Sun, 12 Jul 2020 16:35:29 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=22 Update zmac assembler to version 5jan2019 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=21 <div><strong>Rev 21 - gdevic</strong> (2 file(s) modified)</div><div>Update zmac assembler to version 5jan2019</div>~ /a-z80/trunk/tools/zmac/zmac.exe<br />~ /a-z80/trunk/tools/zmac/zmac.html<br /> gdevic Tue, 05 May 2020 15:23:51 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=21 Revert &quot;Corrected unconnected enable line&quot; in memory_ifc module. ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=20 <div><strong>Rev 20 - gdevic</strong> (2 file(s) modified)</div><div>Revert &quot;Corrected unconnected enable line&quot; in memory_ifc module. Fixes erroneous ...</div>~ /a-z80/trunk/cpu/control/memory_ifc.bdf<br />~ /a-z80/trunk/cpu/control/memory_ifc.v<br /> gdevic Mon, 10 Dec 2018 01:19:18 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=20 Some documentation updates https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=19 <div><strong>Rev 19 - gdevic</strong> (7 file(s) modified)</div><div>Some documentation updates</div>~ /a-z80/trunk/cpu/export.py<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/docs/QuickStart.docx<br />~ /a-z80/trunk/docs/QuickStart.pdf<br />~ /a-z80/trunk/readme.txt<br /> gdevic Wed, 28 Nov 2018 20:55:30 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=19 Correctly latch IO RW wait request Fixed ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=18 <div><strong>Rev 18 - gdevic</strong> (5 file(s) modified)</div><div>Correctly latch IO RW wait request<br /> <br /> Fixed ...</div>~ /a-z80/trunk/cpu/control/memory_ifc.bdf<br />~ /a-z80/trunk/cpu/control/memory_ifc.v<br />+ /a-z80/trunk/cpu/readme.txt<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />~ /a-z80/trunk/readme.txt<br /> gdevic Sat, 24 Feb 2018 06:48:20 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=18 z80: Release 5 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=17 <div><strong>Rev 17 - gdevic</strong> (10 file(s) modified)</div><div>z80: Release 5</div>~ /a-z80/trunk/cpu/bus/data_pins_lattice.v<br />~ /a-z80/trunk/cpu/export.py<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/docs/QuickStart.docx<br />~ /a-z80/trunk/docs/QuickStart.pdf<br />~ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xise<br />~ /a-z80/trunk/host/common/uart.v<br />~ /a-z80/trunk/readme.txt<br /> gdevic Thu, 12 Jan 2017 07:02:24 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=17 Simplify by adding nhold_clk_wait Inverted version is used to feel AND ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=16 <div><strong>Rev 16 - gdevic</strong> (26 file(s) modified)</div><div>Simplify by adding nhold_clk_wait<br /> <br /> Inverted version is used to feel AND ...</div>~ /a-z80/trunk/cpu/alu/alu_flags.bdf<br />~ /a-z80/trunk/cpu/alu/alu_flags.bsf<br />~ /a-z80/trunk/cpu/alu/alu_flags.v<br />~ /a-z80/trunk/cpu/control/clk_delay.bdf<br />~ /a-z80/trunk/cpu/control/clk_delay.bsf<br />~ /a-z80/trunk/cpu/control/clk_delay.v<br />~ /a-z80/trunk/cpu/control/decode_state.bdf<br />~ /a-z80/trunk/cpu/control/decode_state.bsf<br />~ /a-z80/trunk/cpu/control/decode_state.v<br />~ /a-z80/trunk/cpu/control/ir.bdf<br />~ /a-z80/trunk/cpu/control/ir.bsf<br />~ /a-z80/trunk/cpu/control/ir.v<br />~ /a-z80/trunk/cpu/control/memory_ifc.bdf<br />~ /a-z80/trunk/cpu/control/memory_ifc.bsf<br />~ /a-z80/trunk/cpu/control/memory_ifc.v<br />~ /a-z80/trunk/cpu/control/resets.bdf<br />~ /a-z80/trunk/cpu/control/resets.bsf<br />~ /a-z80/trunk/cpu/control/resets.v<br />~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_reset.do<br />~ /a-z80/trunk/cpu/control/test_reset.sv<br />~ /a-z80/trunk/cpu/registers/reg_control.bdf<br />~ /a-z80/trunk/cpu/registers/reg_control.bsf<br />~ /a-z80/trunk/cpu/registers/reg_control.v<br />~ /a-z80/trunk/cpu/registers/test_registers.sv<br />~ /a-z80/trunk/cpu/toplevel/coremodules.vh<br />~ /a-z80/trunk/cpu/toplevel/globals.vh<br /> gdevic Sat, 10 Dec 2016 16:06:34 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=16 zxspectrum: Fix few Quartus warnings https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=15 <div><strong>Rev 15 - gdevic</strong> (2 file(s) modified)</div><div>zxspectrum: Fix few Quartus warnings</div>~ /a-z80/trunk/host/zxspectrum_de1/ula/i2s_intf.vhd<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv<br /> gdevic Sat, 10 Dec 2016 04:55:23 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=15 Add hold_clk_wait to ALU CFL latch This correctly delays latching the ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=14 <div><strong>Rev 14 - gdevic</strong> (5 file(s) modified)</div><div>Add hold_clk_wait to ALU CFL latch<br /> <br /> This correctly delays latching the ...</div>~ /a-z80/trunk/cpu/alu/alu_flags.bdf<br />~ /a-z80/trunk/cpu/alu/alu_flags.bsf<br />~ /a-z80/trunk/cpu/alu/alu_flags.v<br />~ /a-z80/trunk/cpu/toplevel/coremodules.vh<br />~ /a-z80/trunk/host/common/uart.v<br /> gdevic Sat, 10 Dec 2016 04:16:14 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=14 Full support for nWAIT during M1 and memory cycles This set ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=13 <div><strong>Rev 13 - gdevic</strong> (46 file(s) modified)</div><div>Full support for nWAIT during M1 and memory cycles<br /> This set ...</div>+ /a-z80/trunk/cpu/bus/data_pins_lattice.v<br />~ /a-z80/trunk/cpu/control/decode_state.bdf<br />~ /a-z80/trunk/cpu/control/decode_state.bsf<br />~ /a-z80/trunk/cpu/control/decode_state.v<br />~ /a-z80/trunk/cpu/control/execute.bsf<br />~ /a-z80/trunk/cpu/control/execute.v<br />~ /a-z80/trunk/cpu/control/exec_matrix.vh<br />~ /a-z80/trunk/cpu/control/exec_matrix_compiled.vh<br />~ /a-z80/trunk/cpu/control/exec_module.vh<br />~ /a-z80/trunk/cpu/control/exec_zero.vh<br />~ /a-z80/trunk/cpu/control/gencompile.py<br />~ /a-z80/trunk/cpu/control/ir.bdf<br />~ /a-z80/trunk/cpu/control/ir.bsf<br />~ /a-z80/trunk/cpu/control/ir.v<br />~ /a-z80/trunk/cpu/control/memory_ifc.bdf<br />~ /a-z80/trunk/cpu/control/memory_ifc.bsf<br />~ /a-z80/trunk/cpu/control/memory_ifc.v<br />~ /a-z80/trunk/cpu/control/resets.bdf<br />~ /a-z80/trunk/cpu/control/resets.bsf<br />~ /a-z80/trunk/cpu/control/resets.v<br />~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_reset.do<br />~ /a-z80/trunk/cpu/control/test_reset.sv<br />~ /a-z80/trunk/cpu/control/timing_macros.i<br />~ /a-z80/trunk/cpu/export.py<br />~ /a-z80/trunk/cpu/registers/reg_control.bdf<br />~ /a-z80/trunk/cpu/registers/reg_control.bsf<br />~ /a-z80/trunk/cpu/registers/reg_control.v<br />~ /a-z80/trunk/cpu/registers/test_registers.sv<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />~ /a-z80/trunk/cpu/toplevel/coremodules.vh<br />~ /a-z80/trunk/cpu/toplevel/genfuse.py<br />~ /a-z80/trunk/cpu/toplevel/globals.vh<br />~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do<br />~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_top.do<br />~ /a-z80/trunk/cpu/toplevel/test_fuse.vh<br />~ /a-z80/trunk/host/basic_de1/basic_de1.qsf<br />~ /a-z80/trunk/host/basic_de1/basic_de1_fpga.sv<br />~ /a-z80/trunk/host/basic_de1/basic_de1_ModelSim.sv<br />~ /a-z80/trunk/host/basic_de1/simulation/modelsim/test_host.mpf<br />~ /a-z80/trunk/host/basic_de1/simulation/modelsim/wave_host.do<br />+ /a-z80/trunk/host/common/wait_state.bdf<br />+ /a-z80/trunk/host/common/wait_state.bsf<br />+ /a-z80/trunk/host/common/wait_state.v<br />~ /a-z80/trunk/host/zxspectrum_de1/rom/combined.rom<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv<br /> gdevic Fri, 09 Dec 2016 07:38:06 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=13 Explicitly set python to execute within a batch file https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=12 <div><strong>Rev 12 - gdevic</strong> (1 file(s) modified)</div><div>Explicitly set python to execute within a batch file</div>~ /a-z80/trunk/tools/zmac/make_modelsim.bat<br /> gdevic Sat, 26 Nov 2016 15:14:24 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=12 zxspectrum improvements: - Added ZX Spectrum ROM mods as described in ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=11 <div><strong>Rev 11 - gdevic</strong> (5 file(s) modified)</div><div>zxspectrum improvements:<br /> <br /> - Added ZX Spectrum ROM mods as described in ...</div>~ /a-z80/trunk/host/zxspectrum_de1/rom/readme.txt<br />~ /a-z80/trunk/host/zxspectrum_de1/rom/zxspectrum_rom.asm<br />~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qsf<br />+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sdc<br />~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv<br /> gdevic Thu, 28 Apr 2016 05:42:19 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=11 zxspectrum: Various improvements - Fixed keyboard bug (by Bogdan S.) - Minor ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=10 <div><strong>Rev 10 - gdevic</strong> (6 file(s) modified)</div><div>zxspectrum: Various improvements<br /> <br /> - Fixed keyboard bug (by Bogdan S.)<br /> - Minor ...</div>~ /a-z80/trunk/host/zxspectrum_de1/ula/ps2_kbd.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/video.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv<br />~ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv<br /> gdevic Sun, 13 Mar 2016 15:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=10 Updated documentation https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=9 <div><strong>Rev 9 - gdevic</strong> (4 file(s) modified)</div><div>Updated documentation</div>~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/docs/QuickStart.docx<br />~ /a-z80/trunk/docs/QuickStart.pdf<br /> gdevic Sat, 12 Mar 2016 21:34:30 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=9 z80: Release 4 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=8 <div><strong>Rev 8 - gdevic</strong> (318 file(s) modified)</div><div>z80: Release 4</div>~ /a-z80/trunk/cpu/alu/alu_flags.bdf<br />~ /a-z80/trunk/cpu/alu/alu_flags.bsf<br />~ /a-z80/trunk/cpu/alu/alu_flags.v<br />~ /a-z80/trunk/cpu/alu/simulation/modelsim/test_alu.mpf<br />~ /a-z80/trunk/cpu/bus/address_latch.bdf<br />~ /a-z80/trunk/cpu/bus/address_latch.bsf<br />~ /a-z80/trunk/cpu/bus/address_latch.v<br />~ /a-z80/trunk/cpu/bus/bus_control.bdf<br />~ /a-z80/trunk/cpu/bus/bus_control.bsf<br />~ /a-z80/trunk/cpu/bus/bus_control.v<br />- /a-z80/trunk/cpu/bus/bus_switch.sv<br />+ /a-z80/trunk/cpu/bus/bus_switch.v<br />~ /a-z80/trunk/cpu/bus/data_pins.bdf<br />~ /a-z80/trunk/cpu/bus/data_pins.bsf<br />~ /a-z80/trunk/cpu/bus/data_pins.v<br />~ /a-z80/trunk/cpu/bus/simulation/modelsim/test_bus.mpf<br />~ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_bus.do<br />~ /a-z80/trunk/cpu/bus/test_bus.qsf<br />~ /a-z80/trunk/cpu/bus/test_bus.sv<br />~ /a-z80/trunk/cpu/bus/test_pins.sv<br />~ /a-z80/trunk/cpu/control/clk_delay.bdf<br />~ /a-z80/trunk/cpu/control/execute.bsf<br />- /a-z80/trunk/cpu/control/execute.sv<br />+ /a-z80/trunk/cpu/control/execute.v<br />~ /a-z80/trunk/cpu/control/exec_matrix.vh<br />+ /a-z80/trunk/cpu/control/exec_matrix_compiled.vh<br />~ /a-z80/trunk/cpu/control/exec_module.vh<br />~ /a-z80/trunk/cpu/control/exec_zero.vh<br />+ /a-z80/trunk/cpu/control/gencompile.py<br />~ /a-z80/trunk/cpu/control/genmatrix.py<br />~ /a-z80/trunk/cpu/control/genref.py<br />~ /a-z80/trunk/cpu/control/interrupts.bdf<br />~ /a-z80/trunk/cpu/control/interrupts.bsf<br />~ /a-z80/trunk/cpu/control/interrupts.v<br />~ /a-z80/trunk/cpu/control/ir.bdf<br />~ /a-z80/trunk/cpu/control/ir.bsf<br />~ /a-z80/trunk/cpu/control/ir.v<br />- /a-z80/trunk/cpu/control/pla_decode.sv<br />+ /a-z80/trunk/cpu/control/pla_decode.v<br />~ /a-z80/trunk/cpu/control/resets.bdf<br />~ /a-z80/trunk/cpu/control/resets.v<br />~ /a-z80/trunk/cpu/control/sequencer.bdf<br />~ /a-z80/trunk/cpu/control/sequencer.bsf<br />~ /a-z80/trunk/cpu/control/sequencer.v<br />~ /a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf<br />~ /a-z80/trunk/cpu/control/simulation/modelsim/wave_sequencer.do<br />+ /a-z80/trunk/cpu/control/temp_wires.vh<br />~ /a-z80/trunk/cpu/control/test_control.qsf<br />~ /a-z80/trunk/cpu/control/test_decode.sv<br />~ /a-z80/trunk/cpu/control/test_interrupts.sv<br />~ /a-z80/trunk/cpu/control/test_reset.sv<br />~ /a-z80/trunk/cpu/control/test_sequencer.sv<br />~ /a-z80/trunk/cpu/control/Timings.csv<br />~ /a-z80/trunk/cpu/control/Timings.xlsm<br />~ /a-z80/trunk/cpu/control/timing_macros.i<br />+ /a-z80/trunk/cpu/copyleft.txt<br />- /a-z80/trunk/cpu/deploy<br />+ /a-z80/trunk/cpu/export.py<br />~ /a-z80/trunk/cpu/registers/reg_control.bdf<br />~ /a-z80/trunk/cpu/registers/reg_control.bsf<br />~ /a-z80/trunk/cpu/registers/reg_control.v<br />~ /a-z80/trunk/cpu/registers/reg_file.bdf<br />~ /a-z80/trunk/cpu/registers/reg_file.bsf<br />~ /a-z80/trunk/cpu/registers/reg_file.v<br />~ /a-z80/trunk/cpu/registers/simulation/modelsim/test_registers.mpf<br />~ /a-z80/trunk/cpu/registers/simulation/modelsim/wave_registers.do<br />~ /a-z80/trunk/cpu/registers/test_regfile.sv<br />~ /a-z80/trunk/cpu/registers/test_registers.sv<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />~ /a-z80/trunk/cpu/toplevel/core.vh<br />+ /a-z80/trunk/cpu/toplevel/coremodules.vh<br />+ /a-z80/trunk/cpu/toplevel/gencoremodules.py<br />~ /a-z80/trunk/cpu/toplevel/genfuse.py<br />~ /a-z80/trunk/cpu/toplevel/genglobals.py<br />~ /a-z80/trunk/cpu/toplevel/globals.vh<br />~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/test_top.mpf<br />~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_fuse.do<br />~ /a-z80/trunk/cpu/toplevel/simulation/modelsim/wave_top.do<br />~ /a-z80/trunk/cpu/toplevel/test_fuse.vh<br />~ /a-z80/trunk/cpu/toplevel/test_top.sv<br />~ /a-z80/trunk/cpu/toplevel/toplevel.bdf<br />- /a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv<br />+ /a-z80/trunk/cpu/toplevel/z80_top_direct_n.v<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />+ /a-z80/trunk/docs/pdf<br />+ /a-z80/trunk/docs/pdf/a-z80-toplevel.pdf<br />+ /a-z80/trunk/docs/pdf/address_latch.pdf<br />+ /a-z80/trunk/docs/pdf/address_mux.pdf<br />+ /a-z80/trunk/docs/pdf/address_pins.pdf<br />+ /a-z80/trunk/docs/pdf/alu.pdf<br />+ /a-z80/trunk/docs/pdf/alu_bit_select.pdf<br />+ /a-z80/trunk/docs/pdf/alu_control.pdf<br />+ /a-z80/trunk/docs/pdf/alu_core.pdf<br />+ /a-z80/trunk/docs/pdf/alu_flags.pdf<br />+ /a-z80/trunk/docs/pdf/alu_mux_2.pdf<br />+ /a-z80/trunk/docs/pdf/alu_mux_2z.pdf<br />+ /a-z80/trunk/docs/pdf/alu_mux_3z.pdf<br />+ /a-z80/trunk/docs/pdf/alu_mux_4.pdf<br />+ /a-z80/trunk/docs/pdf/alu_mux_8.pdf<br />+ /a-z80/trunk/docs/pdf/alu_prep_daa.pdf<br />+ /a-z80/trunk/docs/pdf/alu_select.pdf<br />+ /a-z80/trunk/docs/pdf/alu_shifter_core.pdf<br />+ /a-z80/trunk/docs/pdf/alu_slice.pdf<br />+ /a-z80/trunk/docs/pdf/bus_control.pdf<br />+ /a-z80/trunk/docs/pdf/clk_delay.pdf<br />+ /a-z80/trunk/docs/pdf/control_pins_n.pdf<br />+ /a-z80/trunk/docs/pdf/data_pins.pdf<br />+ /a-z80/trunk/docs/pdf/data_switch.pdf<br />+ /a-z80/trunk/docs/pdf/data_switch_mask.pdf<br />+ /a-z80/trunk/docs/pdf/decode_state.pdf<br />+ /a-z80/trunk/docs/pdf/inc_dec.pdf<br />+ /a-z80/trunk/docs/pdf/inc_dec_2bit.pdf<br />+ /a-z80/trunk/docs/pdf/interrupts.pdf<br />+ /a-z80/trunk/docs/pdf/ir.pdf<br />+ /a-z80/trunk/docs/pdf/memory_ifc.pdf<br />+ /a-z80/trunk/docs/pdf/pin_control.pdf<br />+ /a-z80/trunk/docs/pdf/reg_control.pdf<br />+ /a-z80/trunk/docs/pdf/reg_file.pdf<br />+ /a-z80/trunk/docs/pdf/reg_latch.pdf<br />+ /a-z80/trunk/docs/pdf/resets.pdf<br />+ /a-z80/trunk/docs/pdf/sequencer.pdf<br />- /a-z80/trunk/docs/png/z80-address_latch.png<br />- /a-z80/trunk/docs/png/z80-address_mux.png<br />~ /a-z80/trunk/docs/png/z80-address_pins.png<br />~ /a-z80/trunk/docs/png/z80-alu.png<br />~ /a-z80/trunk/docs/png/z80-alu_bit_select.png<br />~ /a-z80/trunk/docs/png/z80-alu_control.png<br />~ /a-z80/trunk/docs/png/z80-alu_core.png<br />~ /a-z80/trunk/docs/png/z80-alu_flags.png<br />~ /a-z80/trunk/docs/png/z80-alu_mux_2.png<br />~ /a-z80/trunk/docs/png/z80-alu_mux_2z.png<br />~ /a-z80/trunk/docs/png/z80-alu_mux_3z.png<br />~ /a-z80/trunk/docs/png/z80-alu_mux_4.png<br />~ /a-z80/trunk/docs/png/z80-alu_mux_8.png<br />~ /a-z80/trunk/docs/png/z80-alu_prep_daa.png<br />~ /a-z80/trunk/docs/png/z80-alu_select.png<br />~ /a-z80/trunk/docs/png/z80-alu_shifter_core.png<br />~ /a-z80/trunk/docs/png/z80-alu_slice.png<br />~ /a-z80/trunk/docs/png/z80-bus_control.png<br />~ /a-z80/trunk/docs/png/z80-clk_delay.png<br />~ /a-z80/trunk/docs/png/z80-control_pins_n.png<br />~ /a-z80/trunk/docs/png/z80-data_pins.png<br />~ /a-z80/trunk/docs/png/z80-data_switch.png<br />~ /a-z80/trunk/docs/png/z80-data_switch_mask.png<br />~ /a-z80/trunk/docs/png/z80-decode_state.png<br />~ /a-z80/trunk/docs/png/z80-inc_dec.png<br />~ /a-z80/trunk/docs/png/z80-inc_dec_2bit.png<br />~ /a-z80/trunk/docs/png/z80-interrupts.png<br />~ /a-z80/trunk/docs/png/z80-ir.png<br />~ /a-z80/trunk/docs/png/z80-memory_ifc.png<br />~ /a-z80/trunk/docs/png/z80-pin_control.png<br />~ /a-z80/trunk/docs/png/z80-reg_control.png<br />~ /a-z80/trunk/docs/png/z80-reg_file.png<br />~ /a-z80/trunk/docs/png/z80-reg_latch.png<br />~ /a-z80/trunk/docs/png/z80-resets.png<br />~ /a-z80/trunk/docs/png/z80-sequencer.png<br />~ /a-z80/trunk/docs/QuickStart.docx<br />~ /a-z80/trunk/docs/QuickStart.pdf<br />- /a-z80/trunk/docs/xps<br />- /a-z80/trunk/host/basic<br />+ /a-z80/trunk/host/basic_de1<br />+ /a-z80/trunk/host/basic_de1/basic_de1.qpf<br />+ /a-z80/trunk/host/basic_de1/basic_de1.qsf<br />+ /a-z80/trunk/host/basic_de1/basic_de1.sdc<br />+ /a-z80/trunk/host/basic_de1/basic_de1_fpga.sv<br />+ /a-z80/trunk/host/basic_de1/basic_de1_ModelSim.sv<br />+ /a-z80/trunk/host/basic_de1/fpga.hex<br />+ /a-z80/trunk/host/basic_de1/pll.ppf<br />+ /a-z80/trunk/host/basic_de1/pll.qip<br />+ /a-z80/trunk/host/basic_de1/pll.v<br />+ /a-z80/trunk/host/basic_de1/ram.qip<br />+ /a-z80/trunk/host/basic_de1/ram.v<br />+ /a-z80/trunk/host/basic_de1/readme.txt<br />+ /a-z80/trunk/host/basic_de1/simulation<br />+ /a-z80/trunk/host/basic_de1/simulation/modelsim<br />+ /a-z80/trunk/host/basic_de1/simulation/modelsim/fpga.hex<br />+ /a-z80/trunk/host/basic_de1/simulation/modelsim/r<br />+ /a-z80/trunk/host/basic_de1/simulation/modelsim/test_host.mpf<br />+ /a-z80/trunk/host/basic_de1/simulation/modelsim/wave_host.do<br />+ /a-z80/trunk/host/basic_de1/test_host.sv<br />+ /a-z80/trunk/host/basic_nexys3<br />+ /a-z80/trunk/host/basic_nexys3/basic_nexys3.xise<br />+ /a-z80/trunk/host/basic_nexys3/basic_nexys3_fpga.v<br />+ /a-z80/trunk/host/basic_nexys3/cscope.cdc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.asy<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.gise<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.ucf<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.v<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.veo<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xco<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock.xise<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.ucf<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.v<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/example_design/clock_exdes.xdc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/implement.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/implement.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_ise.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/planAhead_rdn.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/xst.prj<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/implement/xst.scr<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/clock_tb.v<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simcmds.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_isim.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.do<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_mti.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_ncsim.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/simulate_vcs.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/ucli_commands.key<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/vcs_session.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.do<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/functional/wave.sv<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/clock_tb.v<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/sdf_cmd_file<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simcmds.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_isim.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.bat<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.do<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_mti.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_ncsim.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/simulate_vcs.sh<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/ucli_commands.key<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/vcs_session.tcl<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/clock/simulation/timing/wave.do<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/coregen.cgp<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.asy<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.cdc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints/ila.ucf<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.constraints/ila.xdc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.gise<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ncf<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ngc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.sym<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.ucf<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.v<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.veo<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xco<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xdc<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila.xise<br />+ /a-z80/trunk/host/basic_nexys3/ipcore_dir/ila_xmdf.tcl<br />+ /a-z80/trunk/host/basic_nexys3/Nexys3_master.ucf<br />+ /a-z80/trunk/host/basic_nexys3/ram.v<br />+ /a-z80/trunk/host/basic_nexys3/readme.txt<br />+ /a-z80/trunk/host/basic_nexys3/test_host.v<br />+ /a-z80/trunk/host/basic_nexys3/work<br />+ /a-z80/trunk/host/basic_nexys3/work/ram.mif<br />+ /a-z80/trunk/host/common<br />+ /a-z80/trunk/host/common/uart.v<br />- /a-z80/trunk/host/zxspectrum<br />+ /a-z80/trunk/host/zxspectrum_de1<br />+ /a-z80/trunk/host/zxspectrum_de1/pll.ppf<br />+ /a-z80/trunk/host/zxspectrum_de1/pll.qip<br />+ /a-z80/trunk/host/zxspectrum_de1/pll.v<br />+ /a-z80/trunk/host/zxspectrum_de1/ram16.qip<br />+ /a-z80/trunk/host/zxspectrum_de1/ram16.v<br />+ /a-z80/trunk/host/zxspectrum_de1/readme.txt<br />+ /a-z80/trunk/host/zxspectrum_de1/rom<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/assemble.bat<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/combined.rom<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/gw03.rom<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/readme.txt<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/tasm.exe<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/tasm80.tab<br />+ /a-z80/trunk/host/zxspectrum_de1/rom/zxspectrum_rom.asm<br />+ /a-z80/trunk/host/zxspectrum_de1/ula<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/clocks.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/i2c_loader.vhd<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/i2s_intf.vhd<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.ppf<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.qip<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/pll.v<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/ps2_kbd.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/ram8.qip<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/ram8.v<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/test_scr.hex<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qpf<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.qsf<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/test_ula.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/ula.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/video.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/ula/zx_kbd.sv<br />+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qpf<br />+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.qsf<br />+ /a-z80/trunk/host/zxspectrum_de1/zxspectrum_de1.sv<br />~ /a-z80/trunk/modelsim_pre_commit.py<br />~ /a-z80/trunk/modelsim_setup.py<br />~ /a-z80/trunk/readme.txt<br />~ /a-z80/trunk/resources/connotate-fuse.bat<br />~ /a-z80/trunk/resources/connotate-fuse.py<br />~ /a-z80/trunk/resources/process-pla.py<br />~ /a-z80/trunk/tools/dongle/daa/simulate-daa.py<br />~ /a-z80/trunk/tools/dongle/daa/z80-instruction-test-daa.py<br />~ /a-z80/trunk/tools/dongle/neg/simulate-neg.py<br />~ /a-z80/trunk/tools/dongle/sbc/simulate-sbc.py<br />~ /a-z80/trunk/tools/dongle/sbc/simulate-sub.py<br />~ /a-z80/trunk/tools/readme.txt<br />~ /a-z80/trunk/tools/z80_pla_checker/source/ClassPLA.cs<br />~ /a-z80/trunk/tools/z80_pla_checker/z80_pla_checker.exe<br />+ /a-z80/trunk/tools/zmac/bin2coe.py<br />+ /a-z80/trunk/tools/zmac/bin2mif.py<br />~ /a-z80/trunk/tools/zmac/bindump.py<br />- /a-z80/trunk/tools/zmac/fpga.hex<br />~ /a-z80/trunk/tools/zmac/hello_world.asm<br />~ /a-z80/trunk/tools/zmac/make_fpga.bat<br /> gdevic Sat, 12 Mar 2016 19:27:53 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=8 z80: Fixing repeating INIR/OTIR class of instructions https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=7 <div><strong>Rev 7 - gdevic</strong> (5 file(s) modified)</div><div>z80: Fixing repeating INIR/OTIR class of instructions</div>~ /a-z80/trunk/cpu/control/exec_matrix.vh<br />~ /a-z80/trunk/cpu/control/Timings.csv<br />~ /a-z80/trunk/cpu/control/Timings.xlsm<br />~ /a-z80/trunk/cpu/control/timing_macros.i<br />~ /a-z80/trunk/cpu/deploy/exec_matrix.vh<br /> gdevic Fri, 08 Jan 2016 14:59:26 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=7 Added deployment folder with all files needed to use the ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=6 <div><strong>Rev 6 - gdevic</strong> (73 file(s) modified)</div><div>Added deployment folder with all files needed to use the ...</div>~ /a-z80/trunk/cpu/bus/bus_switch.sv<br />~ /a-z80/trunk/cpu/control/execute.sv<br />- /a-z80/trunk/cpu/control/exec_matrix.i<br />+ /a-z80/trunk/cpu/control/exec_matrix.vh<br />- /a-z80/trunk/cpu/control/exec_module.i<br />+ /a-z80/trunk/cpu/control/exec_module.vh<br />- /a-z80/trunk/cpu/control/exec_zero.i<br />+ /a-z80/trunk/cpu/control/exec_zero.vh<br />~ /a-z80/trunk/cpu/control/genmatrix.py<br />~ /a-z80/trunk/cpu/control/genref.py<br />~ /a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf<br />~ /a-z80/trunk/cpu/control/timing_macros.i<br />+ /a-z80/trunk/cpu/deploy<br />+ /a-z80/trunk/cpu/deploy/address_latch.v<br />+ /a-z80/trunk/cpu/deploy/address_mux.v<br />+ /a-z80/trunk/cpu/deploy/address_pins.v<br />+ /a-z80/trunk/cpu/deploy/alu.v<br />+ /a-z80/trunk/cpu/deploy/alu_bit_select.v<br />+ /a-z80/trunk/cpu/deploy/alu_control.v<br />+ /a-z80/trunk/cpu/deploy/alu_core.v<br />+ /a-z80/trunk/cpu/deploy/alu_flags.v<br />+ /a-z80/trunk/cpu/deploy/alu_mux_2.v<br />+ /a-z80/trunk/cpu/deploy/alu_mux_2z.v<br />+ /a-z80/trunk/cpu/deploy/alu_mux_3z.v<br />+ /a-z80/trunk/cpu/deploy/alu_mux_4.v<br />+ /a-z80/trunk/cpu/deploy/alu_mux_8.v<br />+ /a-z80/trunk/cpu/deploy/alu_prep_daa.v<br />+ /a-z80/trunk/cpu/deploy/alu_select.v<br />+ /a-z80/trunk/cpu/deploy/alu_shifter_core.v<br />+ /a-z80/trunk/cpu/deploy/alu_slice.v<br />+ /a-z80/trunk/cpu/deploy/bus_control.v<br />+ /a-z80/trunk/cpu/deploy/bus_switch.sv<br />+ /a-z80/trunk/cpu/deploy/clk_delay.v<br />+ /a-z80/trunk/cpu/deploy/control_pins_n.v<br />+ /a-z80/trunk/cpu/deploy/core.vh<br />+ /a-z80/trunk/cpu/deploy/data_pins.v<br />+ /a-z80/trunk/cpu/deploy/data_switch.v<br />+ /a-z80/trunk/cpu/deploy/data_switch_mask.v<br />+ /a-z80/trunk/cpu/deploy/decode_state.v<br />+ /a-z80/trunk/cpu/deploy/execute.sv<br />+ /a-z80/trunk/cpu/deploy/exec_matrix.vh<br />+ /a-z80/trunk/cpu/deploy/exec_module.vh<br />+ /a-z80/trunk/cpu/deploy/exec_zero.vh<br />+ /a-z80/trunk/cpu/deploy/globals.vh<br />+ /a-z80/trunk/cpu/deploy/inc_dec.v<br />+ /a-z80/trunk/cpu/deploy/inc_dec_2bit.v<br />+ /a-z80/trunk/cpu/deploy/interrupts.v<br />+ /a-z80/trunk/cpu/deploy/ir.v<br />+ /a-z80/trunk/cpu/deploy/memory_ifc.v<br />+ /a-z80/trunk/cpu/deploy/pin_control.v<br />+ /a-z80/trunk/cpu/deploy/pla_decode.sv<br />+ /a-z80/trunk/cpu/deploy/readme.txt<br />+ /a-z80/trunk/cpu/deploy/reg_control.v<br />+ /a-z80/trunk/cpu/deploy/reg_file.v<br />+ /a-z80/trunk/cpu/deploy/reg_latch.v<br />+ /a-z80/trunk/cpu/deploy/resets.v<br />+ /a-z80/trunk/cpu/deploy/sequencer.v<br />+ /a-z80/trunk/cpu/deploy/z80_top_direct_n.sv<br />~ /a-z80/trunk/cpu/top-level-files.txt<br />- /a-z80/trunk/cpu/toplevel/core.i<br />+ /a-z80/trunk/cpu/toplevel/core.vh<br />~ /a-z80/trunk/cpu/toplevel/genfuse.py<br />~ /a-z80/trunk/cpu/toplevel/genglobals.py<br />- /a-z80/trunk/cpu/toplevel/globals.i<br />+ /a-z80/trunk/cpu/toplevel/globals.vh<br />- /a-z80/trunk/cpu/toplevel/test_fuse.i<br />~ /a-z80/trunk/cpu/toplevel/test_fuse.sv<br />+ /a-z80/trunk/cpu/toplevel/test_fuse.vh<br />~ /a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv<br />~ /a-z80/trunk/cpu/toplevel/z80_top_ifc_n.sv<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.qsf<br /> gdevic Fri, 23 Jan 2015 04:40:58 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=6 zxspectrum: Various improvements - Added &quot;Turbo&quot; speed mode switch (SW2) - ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=5 <div><strong>Rev 5 - gdevic</strong> (9 file(s) modified)</div><div>zxspectrum: Various improvements<br /> <br /> - Added &quot;Turbo&quot; speed mode switch (SW2)<br /> - Turbo ...</div>~ /a-z80/trunk/docs/A-Z80_UsersGuide.docx<br />~ /a-z80/trunk/docs/A-Z80_UsersGuide.pdf<br />~ /a-z80/trunk/host/zxspectrum/rom/readme.txt<br />~ /a-z80/trunk/host/zxspectrum/ula/clocks.sv<br />~ /a-z80/trunk/host/zxspectrum/ula/ula.sv<br />~ /a-z80/trunk/host/zxspectrum/ula/zx_kbd.sv<br />~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.qsf<br />~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.sdc<br />~ /a-z80/trunk/host/zxspectrum/zxspectrum_board.sv<br /> gdevic Wed, 24 Dec 2014 15:35:08 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=5 - New directory structure - Added documentation files (and PDF versions) - ... https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=3 <div><strong>Rev 3 - gdevic</strong> (456 file(s) modified)</div><div>- New directory structure<br /> - Added documentation files (and PDF versions)<br /> - ...</div>- /a-z80/cpu<br />- /a-z80/docs<br />- /a-z80/host<br />- /a-z80/resources<br />- /a-z80/tools<br />+ /a-z80/trunk/.gitignore<br />+ /a-z80/trunk/cpu<br />+ /a-z80/trunk/cpu/alu<br />+ /a-z80/trunk/cpu/alu/alu.bdf<br />+ /a-z80/trunk/cpu/alu/alu.bsf<br />+ /a-z80/trunk/cpu/alu/alu.v<br />+ /a-z80/trunk/cpu/alu/alu_bit_select.bdf<br />+ /a-z80/trunk/cpu/alu/alu_bit_select.bsf<br />+ /a-z80/trunk/cpu/alu/alu_bit_select.v<br />+ /a-z80/trunk/cpu/alu/alu_control.bdf<br />+ /a-z80/trunk/cpu/alu/alu_control.bsf<br />+ /a-z80/trunk/cpu/alu/alu_control.v<br />+ /a-z80/trunk/cpu/alu/alu_core.bdf<br />+ /a-z80/trunk/cpu/alu/alu_core.bsf<br />+ /a-z80/trunk/cpu/alu/alu_core.v<br />+ /a-z80/trunk/cpu/alu/alu_flags.bdf<br />+ /a-z80/trunk/cpu/alu/alu_flags.bsf<br />+ /a-z80/trunk/cpu/alu/alu_flags.v<br />+ /a-z80/trunk/cpu/alu/alu_mux_2.bdf<br />+ /a-z80/trunk/cpu/alu/alu_mux_2.bsf<br />+ /a-z80/trunk/cpu/alu/alu_mux_2.v<br />+ /a-z80/trunk/cpu/alu/alu_mux_2z.bdf<br />+ /a-z80/trunk/cpu/alu/alu_mux_2z.bsf<br />+ /a-z80/trunk/cpu/alu/alu_mux_2z.v<br />+ /a-z80/trunk/cpu/alu/alu_mux_3z.bdf<br />+ /a-z80/trunk/cpu/alu/alu_mux_3z.bsf<br />+ /a-z80/trunk/cpu/alu/alu_mux_3z.v<br />+ /a-z80/trunk/cpu/alu/alu_mux_4.bdf<br />+ /a-z80/trunk/cpu/alu/alu_mux_4.bsf<br />+ /a-z80/trunk/cpu/alu/alu_mux_4.v<br />+ /a-z80/trunk/cpu/alu/alu_mux_8.bdf<br />+ /a-z80/trunk/cpu/alu/alu_mux_8.bsf<br />+ /a-z80/trunk/cpu/alu/alu_mux_8.v<br />+ /a-z80/trunk/cpu/alu/alu_prep_daa.bdf<br />+ /a-z80/trunk/cpu/alu/alu_prep_daa.bsf<br />+ /a-z80/trunk/cpu/alu/alu_prep_daa.v<br />+ /a-z80/trunk/cpu/alu/alu_select.bdf<br />+ /a-z80/trunk/cpu/alu/alu_select.bsf<br />+ /a-z80/trunk/cpu/alu/alu_select.v<br />+ /a-z80/trunk/cpu/alu/alu_shifter_core.bdf<br />+ /a-z80/trunk/cpu/alu/alu_shifter_core.bsf<br />+ /a-z80/trunk/cpu/alu/alu_shifter_core.v<br />+ /a-z80/trunk/cpu/alu/alu_slice.bdf<br />+ /a-z80/trunk/cpu/alu/alu_slice.bsf<br />+ /a-z80/trunk/cpu/alu/alu_slice.v<br />+ /a-z80/trunk/cpu/alu/simulation<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/r<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/test_alu.mpf<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_alu.do<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_core.do<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_mux_3z.do<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_prep_daa.do<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_shifter_core.do<br />+ /a-z80/trunk/cpu/alu/simulation/modelsim/wave_slice.do<br />+ /a-z80/trunk/cpu/alu/test_alu.qpf<br />+ /a-z80/trunk/cpu/alu/test_alu.qsf<br />+ /a-z80/trunk/cpu/alu/test_alu.sv<br />+ /a-z80/trunk/cpu/alu/test_core.sv<br />+ /a-z80/trunk/cpu/alu/test_mux_3z.sv<br />+ /a-z80/trunk/cpu/alu/test_prep_daa.sv<br />+ /a-z80/trunk/cpu/alu/test_shifter_core.sv<br />+ /a-z80/trunk/cpu/alu/test_slice.sv<br />+ /a-z80/trunk/cpu/bus<br />+ /a-z80/trunk/cpu/bus/address_latch.bdf<br />+ /a-z80/trunk/cpu/bus/address_latch.bsf<br />+ /a-z80/trunk/cpu/bus/address_latch.v<br />+ /a-z80/trunk/cpu/bus/address_mux.bdf<br />+ /a-z80/trunk/cpu/bus/address_mux.bsf<br />+ /a-z80/trunk/cpu/bus/address_mux.v<br />+ /a-z80/trunk/cpu/bus/address_pins.bdf<br />+ /a-z80/trunk/cpu/bus/address_pins.bsf<br />+ /a-z80/trunk/cpu/bus/address_pins.v<br />+ /a-z80/trunk/cpu/bus/bus_control.bdf<br />+ /a-z80/trunk/cpu/bus/bus_control.bsf<br />+ /a-z80/trunk/cpu/bus/bus_control.v<br />+ /a-z80/trunk/cpu/bus/bus_switch.bsf<br />+ /a-z80/trunk/cpu/bus/bus_switch.sv<br />+ /a-z80/trunk/cpu/bus/control_pins_n.bdf<br />+ /a-z80/trunk/cpu/bus/control_pins_n.bsf<br />+ /a-z80/trunk/cpu/bus/control_pins_n.v<br />+ /a-z80/trunk/cpu/bus/data_pins.bdf<br />+ /a-z80/trunk/cpu/bus/data_pins.bsf<br />+ /a-z80/trunk/cpu/bus/data_pins.v<br />+ /a-z80/trunk/cpu/bus/data_switch.bdf<br />+ /a-z80/trunk/cpu/bus/data_switch.bsf<br />+ /a-z80/trunk/cpu/bus/data_switch.v<br />+ /a-z80/trunk/cpu/bus/data_switch_mask.bdf<br />+ /a-z80/trunk/cpu/bus/data_switch_mask.bsf<br />+ /a-z80/trunk/cpu/bus/data_switch_mask.v<br />+ /a-z80/trunk/cpu/bus/inc_dec.bdf<br />+ /a-z80/trunk/cpu/bus/inc_dec.bsf<br />+ /a-z80/trunk/cpu/bus/inc_dec.v<br />+ /a-z80/trunk/cpu/bus/inc_dec_2bit.bdf<br />+ /a-z80/trunk/cpu/bus/inc_dec_2bit.bsf<br />+ /a-z80/trunk/cpu/bus/inc_dec_2bit.v<br />+ /a-z80/trunk/cpu/bus/simulation<br />+ /a-z80/trunk/cpu/bus/simulation/modelsim<br />+ /a-z80/trunk/cpu/bus/simulation/modelsim/r<br />+ /a-z80/trunk/cpu/bus/simulation/modelsim/test_bus.mpf<br />+ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_bus.do<br />+ /a-z80/trunk/cpu/bus/simulation/modelsim/wave_pins.do<br />+ /a-z80/trunk/cpu/bus/test_bus.qpf<br />+ /a-z80/trunk/cpu/bus/test_bus.qsf<br />+ /a-z80/trunk/cpu/bus/test_bus.sv<br />+ /a-z80/trunk/cpu/bus/test_pins.sv<br />+ /a-z80/trunk/cpu/control<br />+ /a-z80/trunk/cpu/control/clk_delay.bdf<br />+ /a-z80/trunk/cpu/control/clk_delay.bsf<br />+ /a-z80/trunk/cpu/control/clk_delay.v<br />+ /a-z80/trunk/cpu/control/decode_state.bdf<br />+ /a-z80/trunk/cpu/control/decode_state.bsf<br />+ /a-z80/trunk/cpu/control/decode_state.v<br />+ /a-z80/trunk/cpu/control/execute.bsf<br />+ /a-z80/trunk/cpu/control/execute.sv<br />+ /a-z80/trunk/cpu/control/exec_matrix.i<br />+ /a-z80/trunk/cpu/control/exec_module.i<br />+ /a-z80/trunk/cpu/control/exec_zero.i<br />+ /a-z80/trunk/cpu/control/genmatrix.py<br />+ /a-z80/trunk/cpu/control/genref.py<br />+ /a-z80/trunk/cpu/control/interrupts.bdf<br />+ /a-z80/trunk/cpu/control/interrupts.bsf<br />+ /a-z80/trunk/cpu/control/interrupts.v<br />+ /a-z80/trunk/cpu/control/ir.bdf<br />+ /a-z80/trunk/cpu/control/ir.bsf<br />+ /a-z80/trunk/cpu/control/ir.v<br />+ /a-z80/trunk/cpu/control/memory_ifc.bdf<br />+ /a-z80/trunk/cpu/control/memory_ifc.bsf<br />+ /a-z80/trunk/cpu/control/memory_ifc.v<br />+ /a-z80/trunk/cpu/control/pin_control.bdf<br />+ /a-z80/trunk/cpu/control/pin_control.bsf<br />+ /a-z80/trunk/cpu/control/pin_control.v<br />+ /a-z80/trunk/cpu/control/pla_decode.bsf<br />+ /a-z80/trunk/cpu/control/pla_decode.sv<br />+ /a-z80/trunk/cpu/control/resets.bdf<br />+ /a-z80/trunk/cpu/control/resets.bsf<br />+ /a-z80/trunk/cpu/control/resets.v<br />+ /a-z80/trunk/cpu/control/sequencer.bdf<br />+ /a-z80/trunk/cpu/control/sequencer.bsf<br />+ /a-z80/trunk/cpu/control/sequencer.v<br />+ /a-z80/trunk/cpu/control/simulation<br />+ /a-z80/trunk/cpu/control/simulation/modelsim<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/r<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/wave_interrupts.do<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/wave_pin_control.do<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/wave_reset.do<br />+ /a-z80/trunk/cpu/control/simulation/modelsim/wave_sequencer.do<br />+ /a-z80/trunk/cpu/control/test_control.qpf<br />+ /a-z80/trunk/cpu/control/test_control.qsf<br />+ /a-z80/trunk/cpu/control/test_decode.sv<br />+ /a-z80/trunk/cpu/control/test_interrupts.sv<br />+ /a-z80/trunk/cpu/control/test_pin_control.sv<br />+ /a-z80/trunk/cpu/control/test_reset.sv<br />+ /a-z80/trunk/cpu/control/test_sequencer.sv<br />+ /a-z80/trunk/cpu/control/Timings.csv<br />+ /a-z80/trunk/cpu/control/Timings.xlsm<br />+ /a-z80/trunk/cpu/control/timing_macros.i<br />+ /a-z80/trunk/cpu/registers<br />+ /a-z80/trunk/cpu/registers/reg_control.bdf<br />+ /a-z80/trunk/cpu/registers/reg_control.bsf<br />+ /a-z80/trunk/cpu/registers/reg_control.v<br />+ /a-z80/trunk/cpu/registers/reg_file.bdf<br />+ /a-z80/trunk/cpu/registers/reg_file.bsf<br />+ /a-z80/trunk/cpu/registers/reg_file.v<br />+ /a-z80/trunk/cpu/registers/reg_latch.bdf<br />+ /a-z80/trunk/cpu/registers/reg_latch.bsf<br />+ /a-z80/trunk/cpu/registers/reg_latch.v<br />+ /a-z80/trunk/cpu/registers/simulation<br />+ /a-z80/trunk/cpu/registers/simulation/modelsim<br />+ /a-z80/trunk/cpu/registers/simulation/modelsim/r<br />+ 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gdevic Thu, 18 Dec 2014 14:37:35 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=3 The project and the structure was created https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=1 <div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /a-z80<br />+ /a-z80/branches<br />+ /a-z80/tags<br />+ /a-z80/trunk<br /> root Fri, 12 Dec 2014 07:45:03 +0100 https://opencores.org/websvn//websvn/revision?repname=a-z80&path=%2Fa-z80%2Ftrunk%2F&rev=1
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