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can WebSVN RSS feed - can https://opencores.org/websvn//websvn/listing?repname=can&path=%2Fcan%2Ftrunk%2F& Fri, 12 Apr 2024 17:46:31 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Fcan%2Ftrunk%2F&rev=161 <div><strong>Rev 161 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /can<br />+ /can/branches<br />+ /can/tags<br />+ /can/trunk<br />+ /can/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 19:41:31 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Fcan%2Ftrunk%2F&rev=161 New tests for testing the bus-off. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=160 <div><strong>Rev 160 - igorm</strong> (2 file(s) modified)</div><div>New tests for testing the bus-off.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/bench/verilog/can_testbench_defines.v<br /> igorm Tue, 25 Apr 2006 13:17:59 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=160 *** empty log message *** https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=159 <div><strong>Rev 159 - igorm</strong> (2 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/sim/rtl_sim/run/run_sim.scr<br />~ /trunk/sim/rtl_sim/run/wave.do<br /> igorm Mon, 11 Jul 2005 12:49:59 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=159 Fixing overrun problems. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=158 <div><strong>Rev 158 - igorm</strong> (1 file(s) modified)</div><div>Fixing overrun problems.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Mon, 11 Jul 2005 10:25:13 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=158 In &quot;Extended mode&quot; when dual filter was used and standard ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=157 <div><strong>Rev 157 - igorm</strong> (1 file(s) modified)</div><div>In &quot;Extended mode&quot; when dual filter was used and standard ...</div>~ /trunk/rtl/verilog/can_acf.v<br /> igorm Fri, 08 Apr 2005 13:03:07 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=157 Wake-up interrupt was generated in some cases. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=156 <div><strong>Rev 156 - igorm</strong> (1 file(s) modified)</div><div>Wake-up interrupt was generated in some cases.</div>~ /trunk/rtl/verilog/can_registers.v<br /> igorm Fri, 18 Mar 2005 15:04:05 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=156 rd_info_pointer fixed (fifo_empty was used instead of info_empty). https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=155 <div><strong>Rev 155 - igorm</strong> (1 file(s) modified)</div><div>rd_info_pointer fixed (fifo_empty was used instead of info_empty).</div>~ /trunk/rtl/verilog/can_fifo.v<br /> igorm Thu, 10 Mar 2005 08:25:48 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=155 irq is cleared after the release_buffer command. This bug was ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=154 <div><strong>Rev 154 - igorm</strong> (1 file(s) modified)</div><div>irq is cleared after the release_buffer command. This bug was ...</div>~ /trunk/rtl/verilog/can_registers.v<br /> igorm Tue, 30 Nov 2004 15:08:26 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=154 Arbitration capture register changed. SW reset (setting the reset_mode bit) doesn't ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=153 <div><strong>Rev 153 - igorm</strong> (1 file(s) modified)</div><div>Arbitration capture register changed. SW reset (setting the reset_mode bit)<br /> doesn't ...</div>~ /trunk/rtl/verilog/can_bsp.v<br /> igorm Mon, 22 Nov 2004 19:18:03 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=153 Fixes for compatibility after the SW reset. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=152 <div><strong>Rev 152 - igorm</strong> (3 file(s) modified)</div><div>Fixes for compatibility after the SW reset.</div>~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_fifo.v<br />~ /trunk/rtl/verilog/can_registers.v<br /> igorm Thu, 18 Nov 2004 12:39:43 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=152 When CAN was reset by setting the reset_mode signal in ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=151 <div><strong>Rev 151 - igorm</strong> (1 file(s) modified)</div><div>When CAN was reset by setting the reset_mode signal in ...</div>~ /trunk/rtl/verilog/can_bsp.v<br /> igorm Mon, 15 Nov 2004 18:23:21 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=151 Fixed synchronization problem in real hardware when 0xf is used ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=149 <div><strong>Rev 149 - igorm</strong> (2 file(s) modified)</div><div>Fixed synchronization problem in real hardware when 0xf is used ...</div>~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_btl.v<br /> igorm Wed, 27 Oct 2004 18:51:37 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=149 Interrupt is always cleared for one clock after the irq ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=147 <div><strong>Rev 147 - igorm</strong> (2 file(s) modified)</div><div>Interrupt is always cleared for one clock after the irq ...</div>~ /trunk/rtl/verilog/can_registers.v<br />~ /trunk/rtl/verilog/can_top.v<br /> igorm Mon, 25 Oct 2004 11:44:47 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=147 Arbitration bug fixed. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=145 <div><strong>Rev 145 - igorm</strong> (1 file(s) modified)</div><div>Arbitration bug fixed.</div>~ /trunk/rtl/verilog/can_bsp.v<br /> igorm Mon, 25 Oct 2004 06:37:51 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=145 Bit acceptance_filter_mode was inverted. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=143 <div><strong>Rev 143 - igorm</strong> (1 file(s) modified)</div><div>Bit acceptance_filter_mode was inverted.</div>~ /trunk/rtl/verilog/can_acf.v<br /> igorm Mon, 31 May 2004 14:46:11 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=143 Core improved to pass all tests with the Bosch VHDL ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=141 <div><strong>Rev 141 - igorm</strong> (6 file(s) modified)</div><div>Core improved to pass all tests with the Bosch VHDL ...</div>~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_btl.v<br />~ /trunk/rtl/verilog/can_defines.v<br />~ /trunk/rtl/verilog/can_registers.v<br />+ /trunk/rtl/verilog/README.txt<br />~ /trunk/sim/rtl_sim/run/run_sim.scr<br /> igorm Wed, 12 May 2004 15:58:43 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=141 I forgot to thange one signal name. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=140 <div><strong>Rev 140 - igorm</strong> (1 file(s) modified)</div><div>I forgot to thange one signal name.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Thu, 18 Mar 2004 17:39:17 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=140 Signal bus_off_on added. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=139 <div><strong>Rev 139 - igorm</strong> (1 file(s) modified)</div><div>Signal bus_off_on added.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Thu, 18 Mar 2004 17:15:26 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=139 Header changed. Address latched to posedge. bus_off_on signal added. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=138 <div><strong>Rev 138 - mohor</strong> (1 file(s) modified)</div><div>Header changed. Address latched to posedge. bus_off_on signal added.</div>~ /trunk/rtl/verilog/can_top.v<br /> mohor Sun, 08 Feb 2004 14:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=138 Header changed. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=137 <div><strong>Rev 137 - mohor</strong> (9 file(s) modified)</div><div>Header changed.</div>~ /trunk/rtl/verilog/can_btl.v<br />~ /trunk/rtl/verilog/can_crc.v<br />~ /trunk/rtl/verilog/can_defines.v<br />~ /trunk/rtl/verilog/can_fifo.v<br />~ /trunk/rtl/verilog/can_ibo.v<br />~ /trunk/rtl/verilog/can_register.v<br />~ /trunk/rtl/verilog/can_register_asyn.v<br />~ /trunk/rtl/verilog/can_register_asyn_syn.v<br />~ /trunk/rtl/verilog/can_register_syn.v<br /> mohor Sun, 08 Feb 2004 14:34:40 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2F&rev=137
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