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can WebSVN RSS feed - can https://opencores.org/websvn//websvn/listing?repname=can&path=%2Fcan%2Ftrunk%2Fbench%2F& Thu, 28 Mar 2024 18:35:21 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Fcan%2Ftrunk%2Fbench%2F&rev=161 <div><strong>Rev 161 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /can<br />+ /can/branches<br />+ /can/tags<br />+ /can/trunk<br />+ /can/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 19:41:31 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Fcan%2Ftrunk%2Fbench%2F&rev=161 New tests for testing the bus-off. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=160 <div><strong>Rev 160 - igorm</strong> (2 file(s) modified)</div><div>New tests for testing the bus-off.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/bench/verilog/can_testbench_defines.v<br /> igorm Tue, 25 Apr 2006 13:17:59 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=160 Fixing overrun problems. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=158 <div><strong>Rev 158 - igorm</strong> (1 file(s) modified)</div><div>Fixing overrun problems.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Mon, 11 Jul 2005 10:25:13 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=158 I forgot to thange one signal name. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=140 <div><strong>Rev 140 - igorm</strong> (1 file(s) modified)</div><div>I forgot to thange one signal name.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Thu, 18 Mar 2004 17:39:17 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=140 Signal bus_off_on added. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=139 <div><strong>Rev 139 - igorm</strong> (1 file(s) modified)</div><div>Signal bus_off_on added.</div>~ /trunk/bench/verilog/can_testbench.v<br /> igorm Thu, 18 Mar 2004 17:15:26 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=139 mbist signals updated according to newest convention https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=130 <div><strong>Rev 130 - markom</strong> (5 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_defines.v<br />~ /trunk/rtl/verilog/can_fifo.v<br />~ /trunk/rtl/verilog/can_top.v<br /> markom Fri, 17 Oct 2003 05:55:20 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=130 Fixing the core to be Bosch VHDL Reference compatible. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=127 <div><strong>Rev 127 - mohor</strong> (5 file(s) modified)</div><div>Fixing the core to be Bosch VHDL Reference compatible.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/bench/verilog/can_testbench_defines.v<br />~ /trunk/sim/rtl_sim/bin/memory_file_list<br />~ /trunk/sim/rtl_sim/run/wave.do<br />~ /trunk/syn/synplicity/can.prj<br /> mohor Tue, 30 Sep 2003 20:54:00 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=127 Artisan RAMs added. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=119 <div><strong>Rev 119 - mohor</strong> (3 file(s) modified)</div><div>Artisan RAMs added.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/sim/rtl_sim/bin/memory_file_list<br />~ /trunk/sim/rtl_sim/run/run_sim.scr<br /> mohor Wed, 20 Aug 2003 10:03:56 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=119 cs_can_i is used only when WISHBONE interface is not used. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=83 <div><strong>Rev 83 - mohor</strong> (1 file(s) modified)</div><div>cs_can_i is used only when WISHBONE interface is not used.</div>~ /trunk/bench/verilog/can_testbench.v<br /> mohor Tue, 17 Jun 2003 15:14:48 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=83 CAN inturrupt is active low. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=68 <div><strong>Rev 68 - mohor</strong> (1 file(s) modified)</div><div>CAN inturrupt is active low.</div>~ /trunk/bench/verilog/can_testbench.v<br /> mohor Wed, 26 Mar 2003 11:25:39 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=68 ALE changes on negedge of clk. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=63 <div><strong>Rev 63 - mohor</strong> (1 file(s) modified)</div><div>ALE changes on negedge of clk.</div>~ /trunk/bench/verilog/can_testbench.v<br /> mohor Fri, 14 Mar 2003 19:37:30 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=63 Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=61 <div><strong>Rev 61 - mohor</strong> (2 file(s) modified)</div><div>Bidirectional port_0_i changed to port_0_io.<br /> input cs_can changed to cs_can_i.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 12 Mar 2003 05:57:36 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=61 rd_i and wr_i are active high signals. If 8051 is ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=60 <div><strong>Rev 60 - mohor</strong> (2 file(s) modified)</div><div>rd_i and wr_i are active high signals. If 8051 is ...</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 12 Mar 2003 04:40:00 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=60 8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=59 <div><strong>Rev 59 - mohor</strong> (3 file(s) modified)</div><div>8051 interface added (besides WISHBONE interface). Selection is made in<br /> can_defines.v ...</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_defines.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 12 Mar 2003 04:19:13 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=59 tx_o is now tristated signal. tx_oen and tx_o combined together. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=52 <div><strong>Rev 52 - mohor</strong> (2 file(s) modified)</div><div>tx_o is now tristated signal. tx_oen and tx_o combined together.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 05 Mar 2003 15:33:37 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=52 Top level signal names changed. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=50 <div><strong>Rev 50 - mohor</strong> (2 file(s) modified)</div><div>Top level signal names changed.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 05 Mar 2003 15:01:56 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=50 Actel APA ram supported. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=48 <div><strong>Rev 48 - mohor</strong> (8 file(s) modified)</div><div>Actel APA ram supported.</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_defines.v<br />~ /trunk/rtl/verilog/can_fifo.v<br />~ /trunk/rtl/verilog/can_top.v<br />+ /trunk/sim/rtl_sim/bin/memory_file_list<br />~ /trunk/sim/rtl_sim/run/run_sim.scr<br />~ /trunk/syn/synplicity/can.prj<br /> mohor Sat, 01 Mar 2003 22:57:12 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=48 CAN core finished. Host interface added. Registers finished. Synchronization to the ... https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=39 <div><strong>Rev 39 - mohor</strong> (5 file(s) modified)</div><div>CAN core finished. Host interface added. Registers finished.<br /> Synchronization to the ...</div>~ /trunk/bench/verilog/can_testbench.v<br />~ /trunk/rtl/verilog/can_bsp.v<br />~ /trunk/rtl/verilog/can_fifo.v<br />~ /trunk/rtl/verilog/can_registers.v<br />~ /trunk/rtl/verilog/can_top.v<br /> mohor Wed, 19 Feb 2003 14:44:03 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=39 Temporary backup version (still fully operable). https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=38 <div><strong>Rev 38 - mohor</strong> (1 file(s) modified)</div><div>Temporary backup version (still fully operable).</div>~ /trunk/bench/verilog/can_testbench.v<br /> mohor Tue, 18 Feb 2003 00:19:39 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=38 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=37 <div><strong>Rev 37 - mohor</strong> (1 file(s) modified)</div><div>Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.</div>~ /trunk/bench/verilog/can_testbench_defines.v<br /> mohor Tue, 18 Feb 2003 00:17:44 +0100 https://opencores.org/websvn//websvn/revision?repname=can&path=%2Ftrunk%2Fbench%2F&rev=37
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