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cpu_lecture WebSVN RSS feed - cpu_lecture https://opencores.org/websvn//websvn/listing?repname=cpu_lecture&path=%2Fcpu_lecture%2F& Thu, 28 Mar 2024 10:47:15 +0100 FeedCreator 1.7.2 fixed fault is BSET/BCLR instruction https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=11 <div><strong>Rev 11 - jsauermann</strong> (1 file(s) modified)</div><div>fixed fault is BSET/BCLR instruction</div>~ /cpu_lecture/trunk/src/alu.vhd<br /> jsauermann Sun, 10 Jan 2010 18:42:17 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=11 wait decoder fault fixed https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=10 <div><strong>Rev 10 - jsauermann</strong> (2 file(s) modified)</div><div>wait decoder fault fixed</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br />~ /cpu_lecture/trunk/src/opc_fetch.vhd<br /> jsauermann Sun, 10 Jan 2010 13:21:19 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=10 renamed 'main' to 'hello' in build commands https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=9 <div><strong>Rev 9 - jsauermann</strong> (1 file(s) modified)</div><div>renamed 'main' to 'hello' in build commands</div>~ /cpu_lecture/trunk/html/09_Toolchain_Setup.html<br /> jsauermann Sat, 09 Jan 2010 17:11:29 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=9 picture quality slightly improved https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=8 <div><strong>Rev 8 - jsauermann</strong> (1 file(s) modified)</div><div>picture quality slightly improved</div>~ /cpu_lecture/trunk/doc/lecture.pdf<br /> jsauermann Sat, 09 Jan 2010 12:29:02 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=8 support multiple port sizes in make_mem https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=7 <div><strong>Rev 7 - jsauermann</strong> (1 file(s) modified)</div><div>support multiple port sizes in make_mem</div>+ /cpu_lecture/trunk/gtkwave.save<br /> jsauermann Sat, 09 Jan 2010 11:15:01 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=7 support multiple port sizes in make_mem https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=6 <div><strong>Rev 6 - jsauermann</strong> (2 file(s) modified)</div><div>support multiple port sizes in make_mem</div>~ /cpu_lecture/trunk/src/prog_mem.vhd<br />~ /cpu_lecture/trunk/src/prog_mem_content.vhd<br /> jsauermann Sat, 09 Jan 2010 10:59:56 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=6 support multiple port sizes in make_mem https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=5 <div><strong>Rev 5 - jsauermann</strong> (1 file(s) modified)</div><div>support multiple port sizes in make_mem</div>~ /cpu_lecture/trunk/tools/make_mem.cc<br /> jsauermann Sat, 09 Jan 2010 10:53:40 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=5 initial check-in https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=4 <div><strong>Rev 4 - jsauermann</strong> (2 file(s) modified)</div><div>initial check-in</div>+ /cpu_lecture/trunk/doc<br />+ /cpu_lecture/trunk/doc/lecture.pdf<br /> jsauermann Tue, 05 Jan 2010 14:38:42 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=4 initial check-in https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=3 <div><strong>Rev 3 - jsauermann</strong> (1 file(s) modified)</div><div>initial check-in</div>+ /cpu_lecture/trunk/Makefile<br /> jsauermann Tue, 05 Jan 2010 09:50:41 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=3 initial check-in https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=2 <div><strong>Rev 2 - jsauermann</strong> (88 file(s) modified)</div><div>initial check-in</div>+ /cpu_lecture/trunk/app<br />+ /cpu_lecture/trunk/app/hello.c<br />+ /cpu_lecture/trunk/app/hello.lss<br />+ /cpu_lecture/trunk/app/hello.lss1<br />+ /cpu_lecture/trunk/html<br />+ /cpu_lecture/trunk/html/01_Introduction_and_Overview.html<br />+ /cpu_lecture/trunk/html/02_Top_Level.html<br />+ /cpu_lecture/trunk/html/03_Pipelining.html<br />+ /cpu_lecture/trunk/html/04_Cpu_Core.html<br />+ /cpu_lecture/trunk/html/05_Opcode_Fetch.html<br />+ /cpu_lecture/trunk/html/06_Data_Path.html<br />+ /cpu_lecture/trunk/html/07_Opcode_Decoder.html<br />+ /cpu_lecture/trunk/html/08_IO.html<br />+ /cpu_lecture/trunk/html/09_Toolchain_Setup.html<br />+ /cpu_lecture/trunk/html/10_Listing_of_alu_vhd.html<br />+ /cpu_lecture/trunk/html/11_Listing_of_avr_fpga.vhd.html<br />+ /cpu_lecture/trunk/html/12_Listing_of_baudgen.vhd.html<br />+ /cpu_lecture/trunk/html/13_Listing_of_common.vhd.html<br />+ /cpu_lecture/trunk/html/14_Listing_of_cpu_core.vhd.html<br />+ /cpu_lecture/trunk/html/15_Listing_of_data_mem.vhd.html<br />+ /cpu_lecture/trunk/html/16_Listing_of_data_path.vhd.html<br />+ /cpu_lecture/trunk/html/17_Listing_of_io.vhd.html<br />+ /cpu_lecture/trunk/html/18_Listing_of_opc_deco.vhd.html<br />+ /cpu_lecture/trunk/html/19_Listing_of_opc_fetch.vhd.html<br />+ /cpu_lecture/trunk/html/20_Listing_of_prog_mem_content.vhd.html<br />+ /cpu_lecture/trunk/html/21_Listing_of_prog_mem.vhd.html<br />+ /cpu_lecture/trunk/html/22_Listing_of_reg_16.vhd.html<br />+ /cpu_lecture/trunk/html/23_Listing_of_register_file.vhd.html<br />+ /cpu_lecture/trunk/html/24_Listing_of_segment7.vhd.html<br />+ /cpu_lecture/trunk/html/25_Listing_of_status_reg.vhd.html<br />+ /cpu_lecture/trunk/html/26_Listing_of_uart_rx.vhd.html<br />+ /cpu_lecture/trunk/html/27_Listing_of_uart_tx.vhd.html<br />+ /cpu_lecture/trunk/html/28_Listing_of_RAMB4_S4_S4.vhd.html<br />+ /cpu_lecture/trunk/html/29_Listing_of_test_tb.vhd.html<br />+ /cpu_lecture/trunk/html/30_Listing_of_avr_fpga.ucf.html<br />+ /cpu_lecture/trunk/html/31_Listing_of_Makefile.html<br />+ /cpu_lecture/trunk/html/32_Listing_of_hello.c.html<br />+ /cpu_lecture/trunk/html/33_Listing_of_make_mem.cc.html<br />+ /cpu_lecture/trunk/html/34_Listing_of_end_conv.cc.html<br />+ /cpu_lecture/trunk/html/avr_fpga.png<br />+ /cpu_lecture/trunk/html/Component_tree.png<br />+ /cpu_lecture/trunk/html/cpu_core_1.png<br />+ /cpu_lecture/trunk/html/cpu_core_2.png<br />+ /cpu_lecture/trunk/html/data_path.png<br />+ /cpu_lecture/trunk/html/data_path_1.png<br />+ /cpu_lecture/trunk/html/data_path_2.png<br />+ /cpu_lecture/trunk/html/GTKWave.png<br />+ /cpu_lecture/trunk/html/index.html<br />+ /cpu_lecture/trunk/html/lecture.css<br />+ /cpu_lecture/trunk/html/opcode_decoder_1.png<br />+ /cpu_lecture/trunk/html/opcode_fetch_1.png<br />+ /cpu_lecture/trunk/html/opcode_fetch_2.png<br />+ /cpu_lecture/trunk/html/pipelining_1.png<br />+ /cpu_lecture/trunk/html/pipelining_2.png<br />+ /cpu_lecture/trunk/html/pipelining_3.png<br />+ /cpu_lecture/trunk/html/toc.html<br />+ /cpu_lecture/trunk/html/toolchain_1.png<br />+ /cpu_lecture/trunk/index.html<br />+ /cpu_lecture/trunk/simu<br />+ /cpu_lecture/trunk/src<br />+ /cpu_lecture/trunk/src/alu.vhd<br />+ /cpu_lecture/trunk/src/avr_fpga.ucf<br />+ /cpu_lecture/trunk/src/avr_fpga.vhd<br />+ /cpu_lecture/trunk/src/baudgen.vhd<br />+ /cpu_lecture/trunk/src/common.vhd<br />+ /cpu_lecture/trunk/src/COPYING<br />+ /cpu_lecture/trunk/src/cpu_core.vhd<br />+ /cpu_lecture/trunk/src/data_mem.vhd<br />+ /cpu_lecture/trunk/src/data_path.vhd<br />+ /cpu_lecture/trunk/src/io.vhd<br />+ /cpu_lecture/trunk/src/opc_deco.vhd<br />+ /cpu_lecture/trunk/src/opc_fetch.vhd<br />+ /cpu_lecture/trunk/src/prog_mem.vhd<br />+ /cpu_lecture/trunk/src/prog_mem_content.vhd<br />+ /cpu_lecture/trunk/src/register_file.vhd<br />+ /cpu_lecture/trunk/src/reg_16.vhd<br />+ /cpu_lecture/trunk/src/segment7.vhd<br />+ /cpu_lecture/trunk/src/status_reg.vhd<br />+ /cpu_lecture/trunk/src/uart.vhd<br />+ /cpu_lecture/trunk/src/uart_rx.vhd<br />+ /cpu_lecture/trunk/src/uart_tx.vhd<br />+ /cpu_lecture/trunk/test<br />+ /cpu_lecture/trunk/test/RAMB4_S4_S4.vhd<br />+ /cpu_lecture/trunk/test/test_tb.vhd<br />+ /cpu_lecture/trunk/tools<br />+ /cpu_lecture/trunk/tools/end_conv.cc<br />+ /cpu_lecture/trunk/tools/make_mem.cc<br />+ /cpu_lecture/trunk/work<br /> jsauermann Mon, 04 Jan 2010 16:51:33 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=2 The project and the structure was created https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=1 <div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /cpu_lecture<br />+ /cpu_lecture/branches<br />+ /cpu_lecture/tags<br />+ /cpu_lecture/trunk<br /> root Mon, 04 Jan 2010 15:40:04 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2F&rev=1
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