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cpu_lecture WebSVN RSS feed - cpu_lecture https://opencores.org/websvn//websvn/listing?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F& Thu, 26 Nov 2020 10:44:17 +0100 FeedCreator 1.7.2 uart transmitter state handling improved https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=25 <div><strong>Rev 25 - jsauermann</strong> (2 file(s) modified)</div><div>uart transmitter state handling improved</div>~ /cpu_lecture/trunk/src/uart.vhd<br />~ /cpu_lecture/trunk/src/uart_tx.vhd<br /> jsauermann Thu, 01 Apr 2010 16:56:26 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=25 write updated SP in interrupt opcode https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=24 <div><strong>Rev 24 - jsauermann</strong> (1 file(s) modified)</div><div>write updated SP in interrupt opcode</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br /> jsauermann Mon, 08 Mar 2010 18:30:05 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=24 fixed bugs in interrupt vector https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=23 <div><strong>Rev 23 - jsauermann</strong> (2 file(s) modified)</div><div>fixed bugs in interrupt vector</div>~ /cpu_lecture/trunk/src/io.vhd<br />~ /cpu_lecture/trunk/src/opc_deco.vhd<br /> jsauermann Sun, 07 Mar 2010 15:26:37 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=23 aligned I/O port numbers to real mega8 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=22 <div><strong>Rev 22 - jsauermann</strong> (1 file(s) modified)</div><div>aligned I/O port numbers to real mega8</div>~ /cpu_lecture/trunk/src/io.vhd<br /> jsauermann Sun, 07 Mar 2010 10:11:01 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=22 fixed bug in Sign bit computation for SUB and CP ... https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=21 <div><strong>Rev 21 - jsauermann</strong> (1 file(s) modified)</div><div>fixed bug in Sign bit computation for SUB and CP ...</div>~ /cpu_lecture/trunk/src/alu.vhd<br /> jsauermann Fri, 05 Mar 2010 16:04:02 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=21 readability of 95xx instructions improved https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=20 <div><strong>Rev 20 - jsauermann</strong> (1 file(s) modified)</div><div>readability of 95xx instructions improved</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br /> jsauermann Mon, 01 Feb 2010 19:10:04 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=20 another bug in the decoding of two-cycle instructions fixed https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=19 <div><strong>Rev 19 - jsauermann</strong> (1 file(s) modified)</div><div>another bug in the decoding of two-cycle instructions fixed</div>~ /cpu_lecture/trunk/src/opc_fetch.vhd<br /> jsauermann Mon, 01 Feb 2010 19:06:05 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=19 fixed a bug that caused double execution of some 95xx ... https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=18 <div><strong>Rev 18 - jsauermann</strong> (1 file(s) modified)</div><div>fixed a bug that caused double execution of some 95xx ...</div>~ /cpu_lecture/trunk/src/opc_fetch.vhd<br /> jsauermann Fri, 29 Jan 2010 16:49:55 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=18 fixed missing carry flag for ROR instruction https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=17 <div><strong>Rev 17 - jsauermann</strong> (1 file(s) modified)</div><div>fixed missing carry flag for ROR instruction</div>~ /cpu_lecture/trunk/src/alu.vhd<br /> jsauermann Mon, 25 Jan 2010 18:41:57 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=17 fixed missing RD_M signal for IN instruction https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=16 <div><strong>Rev 16 - jsauermann</strong> (1 file(s) modified)</div><div>fixed missing RD_M signal for IN instruction</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br /> jsauermann Sat, 16 Jan 2010 17:07:41 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=16 fixed SP auto inc/dec problem https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=15 <div><strong>Rev 15 - jsauermann</strong> (3 file(s) modified)</div><div>fixed SP auto inc/dec problem</div>~ /cpu_lecture/trunk/src/common.vhd<br />~ /cpu_lecture/trunk/src/opc_deco.vhd<br />~ /cpu_lecture/trunk/src/register_file.vhd<br /> jsauermann Sat, 16 Jan 2010 15:12:28 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=15 fixed wrong Q_RSEL for LDD instruction https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=14 <div><strong>Rev 14 - jsauermann</strong> (1 file(s) modified)</div><div>fixed wrong Q_RSEL for LDD instruction</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br /> jsauermann Thu, 14 Jan 2010 18:53:35 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=14 fixed fault in LDD/STD decoding https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=13 <div><strong>Rev 13 - jsauermann</strong> (2 file(s) modified)</div><div>fixed fault in LDD/STD decoding</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br />~ /cpu_lecture/trunk/src/opc_fetch.vhd<br /> jsauermann Wed, 13 Jan 2010 18:59:59 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=13 fixed bug in decoding of I/O address for SP https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=12 <div><strong>Rev 12 - jsauermann</strong> (1 file(s) modified)</div><div>fixed bug in decoding of I/O address for SP</div>~ /cpu_lecture/trunk/src/register_file.vhd<br /> jsauermann Tue, 12 Jan 2010 18:48:59 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=12 fixed fault is BSET/BCLR instruction https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=11 <div><strong>Rev 11 - jsauermann</strong> (1 file(s) modified)</div><div>fixed fault is BSET/BCLR instruction</div>~ /cpu_lecture/trunk/src/alu.vhd<br /> jsauermann Sun, 10 Jan 2010 18:42:17 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=11 wait decoder fault fixed https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=10 <div><strong>Rev 10 - jsauermann</strong> (2 file(s) modified)</div><div>wait decoder fault fixed</div>~ /cpu_lecture/trunk/src/opc_deco.vhd<br />~ /cpu_lecture/trunk/src/opc_fetch.vhd<br /> jsauermann Sun, 10 Jan 2010 13:21:19 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=10 support multiple port sizes in make_mem https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=6 <div><strong>Rev 6 - jsauermann</strong> (2 file(s) modified)</div><div>support multiple port sizes in make_mem</div>~ /cpu_lecture/trunk/src/prog_mem.vhd<br />~ /cpu_lecture/trunk/src/prog_mem_content.vhd<br /> jsauermann Sat, 09 Jan 2010 10:59:56 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=6 initial check-in https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=2 <div><strong>Rev 2 - jsauermann</strong> (88 file(s) modified)</div><div>initial check-in</div>+ /cpu_lecture/trunk/app<br />+ /cpu_lecture/trunk/app/hello.c<br />+ /cpu_lecture/trunk/app/hello.lss<br />+ /cpu_lecture/trunk/app/hello.lss1<br />+ /cpu_lecture/trunk/html<br />+ /cpu_lecture/trunk/html/01_Introduction_and_Overview.html<br />+ /cpu_lecture/trunk/html/02_Top_Level.html<br />+ /cpu_lecture/trunk/html/03_Pipelining.html<br />+ /cpu_lecture/trunk/html/04_Cpu_Core.html<br />+ /cpu_lecture/trunk/html/05_Opcode_Fetch.html<br />+ /cpu_lecture/trunk/html/06_Data_Path.html<br />+ /cpu_lecture/trunk/html/07_Opcode_Decoder.html<br />+ /cpu_lecture/trunk/html/08_IO.html<br />+ /cpu_lecture/trunk/html/09_Toolchain_Setup.html<br />+ /cpu_lecture/trunk/html/10_Listing_of_alu_vhd.html<br />+ /cpu_lecture/trunk/html/11_Listing_of_avr_fpga.vhd.html<br />+ /cpu_lecture/trunk/html/12_Listing_of_baudgen.vhd.html<br />+ /cpu_lecture/trunk/html/13_Listing_of_common.vhd.html<br />+ /cpu_lecture/trunk/html/14_Listing_of_cpu_core.vhd.html<br />+ /cpu_lecture/trunk/html/15_Listing_of_data_mem.vhd.html<br />+ /cpu_lecture/trunk/html/16_Listing_of_data_path.vhd.html<br />+ /cpu_lecture/trunk/html/17_Listing_of_io.vhd.html<br />+ /cpu_lecture/trunk/html/18_Listing_of_opc_deco.vhd.html<br />+ /cpu_lecture/trunk/html/19_Listing_of_opc_fetch.vhd.html<br />+ /cpu_lecture/trunk/html/20_Listing_of_prog_mem_content.vhd.html<br />+ /cpu_lecture/trunk/html/21_Listing_of_prog_mem.vhd.html<br />+ /cpu_lecture/trunk/html/22_Listing_of_reg_16.vhd.html<br />+ /cpu_lecture/trunk/html/23_Listing_of_register_file.vhd.html<br />+ /cpu_lecture/trunk/html/24_Listing_of_segment7.vhd.html<br />+ /cpu_lecture/trunk/html/25_Listing_of_status_reg.vhd.html<br />+ /cpu_lecture/trunk/html/26_Listing_of_uart_rx.vhd.html<br />+ /cpu_lecture/trunk/html/27_Listing_of_uart_tx.vhd.html<br />+ /cpu_lecture/trunk/html/28_Listing_of_RAMB4_S4_S4.vhd.html<br />+ /cpu_lecture/trunk/html/29_Listing_of_test_tb.vhd.html<br />+ /cpu_lecture/trunk/html/30_Listing_of_avr_fpga.ucf.html<br />+ /cpu_lecture/trunk/html/31_Listing_of_Makefile.html<br />+ /cpu_lecture/trunk/html/32_Listing_of_hello.c.html<br />+ /cpu_lecture/trunk/html/33_Listing_of_make_mem.cc.html<br />+ /cpu_lecture/trunk/html/34_Listing_of_end_conv.cc.html<br />+ /cpu_lecture/trunk/html/avr_fpga.png<br />+ /cpu_lecture/trunk/html/Component_tree.png<br />+ /cpu_lecture/trunk/html/cpu_core_1.png<br />+ /cpu_lecture/trunk/html/cpu_core_2.png<br />+ /cpu_lecture/trunk/html/data_path.png<br />+ /cpu_lecture/trunk/html/data_path_1.png<br />+ /cpu_lecture/trunk/html/data_path_2.png<br />+ /cpu_lecture/trunk/html/GTKWave.png<br />+ /cpu_lecture/trunk/html/index.html<br />+ /cpu_lecture/trunk/html/lecture.css<br />+ /cpu_lecture/trunk/html/opcode_decoder_1.png<br />+ /cpu_lecture/trunk/html/opcode_fetch_1.png<br />+ /cpu_lecture/trunk/html/opcode_fetch_2.png<br />+ /cpu_lecture/trunk/html/pipelining_1.png<br />+ /cpu_lecture/trunk/html/pipelining_2.png<br />+ /cpu_lecture/trunk/html/pipelining_3.png<br />+ /cpu_lecture/trunk/html/toc.html<br />+ /cpu_lecture/trunk/html/toolchain_1.png<br />+ /cpu_lecture/trunk/index.html<br />+ /cpu_lecture/trunk/simu<br />+ /cpu_lecture/trunk/src<br />+ /cpu_lecture/trunk/src/alu.vhd<br />+ /cpu_lecture/trunk/src/avr_fpga.ucf<br />+ /cpu_lecture/trunk/src/avr_fpga.vhd<br />+ /cpu_lecture/trunk/src/baudgen.vhd<br />+ /cpu_lecture/trunk/src/common.vhd<br />+ /cpu_lecture/trunk/src/COPYING<br />+ /cpu_lecture/trunk/src/cpu_core.vhd<br />+ /cpu_lecture/trunk/src/data_mem.vhd<br />+ /cpu_lecture/trunk/src/data_path.vhd<br />+ /cpu_lecture/trunk/src/io.vhd<br />+ /cpu_lecture/trunk/src/opc_deco.vhd<br />+ /cpu_lecture/trunk/src/opc_fetch.vhd<br />+ /cpu_lecture/trunk/src/prog_mem.vhd<br />+ /cpu_lecture/trunk/src/prog_mem_content.vhd<br />+ /cpu_lecture/trunk/src/register_file.vhd<br />+ /cpu_lecture/trunk/src/reg_16.vhd<br />+ /cpu_lecture/trunk/src/segment7.vhd<br />+ /cpu_lecture/trunk/src/status_reg.vhd<br />+ /cpu_lecture/trunk/src/uart.vhd<br />+ /cpu_lecture/trunk/src/uart_rx.vhd<br />+ /cpu_lecture/trunk/src/uart_tx.vhd<br />+ /cpu_lecture/trunk/test<br />+ /cpu_lecture/trunk/test/RAMB4_S4_S4.vhd<br />+ /cpu_lecture/trunk/test/test_tb.vhd<br />+ /cpu_lecture/trunk/tools<br />+ /cpu_lecture/trunk/tools/end_conv.cc<br />+ /cpu_lecture/trunk/tools/make_mem.cc<br />+ /cpu_lecture/trunk/work<br /> jsauermann Mon, 04 Jan 2010 16:51:33 +0100 https://opencores.org/websvn//websvn/revision?repname=cpu_lecture&path=%2Fcpu_lecture%2Ftrunk%2Fsrc%2F&rev=2
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