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ethernet_tri_mode WebSVN RSS feed - ethernet_tri_mode https://opencores.org/websvn//websvn/listing?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F& Fri, 06 Dec 2019 16:46:07 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=33 <div><strong>Rev 33 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet_tri_mode<br />+ /ethernet_tri_mode/branches<br />+ /ethernet_tri_mode/tags<br />+ /ethernet_tri_mode/trunk<br />+ /ethernet_tri_mode/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 21:09:34 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=33 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=32 <div><strong>Rev 32 - maverickist</strong> (1 file(s) modified)</div><div>no message</div>~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br /> maverickist Thu, 08 Jan 2009 13:53:34 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=32 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=28 <div><strong>Rev 28 - maverickist</strong> (13 file(s) modified)</div><div>no message</div>~ /trunk/bench/verilog/tb_top.v<br />~ /trunk/bench/verilog/User_int_sim.v<br />+ /trunk/rtl/verilog/afifo.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />~ /trunk/rtl/verilog/MAC_top.v<br />~ /trunk/rtl/verilog/reg_int.v<br />~ /trunk/sim/rtl_sim/modsim_sim/bin/sim.mod<br />~ /trunk/sim/rtl_sim/modsim_sim/bin/vlog-rtl.list<br />~ /trunk/sim/rtl_sim/modsim_sim/data/config.ini<br />~ /trunk/sim/rtl_sim/modsim_sim/data/CPU.vec<br />~ /trunk/sim/rtl_sim/modsim_sim/script/start_verify.tcl<br />~ /trunk/syn/syn_xilinx.prj<br /> maverickist Sun, 17 Aug 2008 11:41:33 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=28 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=23 <div><strong>Rev 23 - maverickist</strong> (6 file(s) modified)</div><div>no message</div>~ /trunk/bench/verilog/Phy_sim.v<br />~ /trunk/bench/verilog/User_int_sim.v<br />~ /trunk/rtl/verilog/MAC_rx.v<br />~ /trunk/rtl/verilog/MAC_tx.v<br />~ /trunk/rtl/verilog/reg_int.v<br />~ /trunk/sim/rtl_sim/ncsim_sim/log/ncsim.log<br /> maverickist Fri, 17 Nov 2006 17:53:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=23 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 <div><strong>Rev 22 - maverickist</strong> (8 file(s) modified)</div><div>no message</div>+ /trunk/rtl/verilog/TECH/altera<br />+ /trunk/rtl/verilog/TECH/altera/CLK_DIV2.v<br />+ /trunk/rtl/verilog/TECH/altera/CLK_SWITCH.v<br />+ /trunk/rtl/verilog/TECH/altera/duram.v<br />+ /trunk/rtl/verilog/TECH/xilinx<br />+ /trunk/rtl/verilog/TECH/xilinx/CLK_DIV2.v<br />+ /trunk/rtl/verilog/TECH/xilinx/CLK_SWITCH.v<br />+ /trunk/rtl/verilog/TECH/xilinx/duram.v<br /> maverickist Sun, 22 Oct 2006 16:12:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=19 <div><strong>Rev 19 - maverickist</strong> (11 file(s) modified)</div><div>no message</div>~ /trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v<br />~ /trunk/rtl/verilog/reg_int.v<br />~ /trunk/rtl/verilog/RMON.v<br />~ /trunk/rtl/verilog/RMON/RMON_addr_gen.v<br />~ /trunk/rtl/verilog/RMON/RMON_ctrl.v<br />- /trunk/rtl/verilog/TECH/afifo.v<br />~ /trunk/sim/rtl_sim/ncsim_sim/data/config.ini<br />~ /trunk/sim/rtl_sim/ncsim_sim/log/ncsim.log<br /> maverickist Sun, 25 Jun 2006 04:59:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=19 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=18 <div><strong>Rev 18 - maverickist</strong> (2 file(s) modified)</div><div>no message</div>~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v<br /> maverickist Sun, 28 May 2006 05:09:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=18 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=14 <div><strong>Rev 14 - maverickist</strong> (2 file(s) modified)</div><div>no message</div>~ /trunk/rtl/verilog/reg_int.v<br />~ /trunk/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl<br /> maverickist Wed, 25 Jan 2006 12:34:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=14 verification is complete. https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=7 <div><strong>Rev 7 - maverickist</strong> (51 file(s) modified)</div><div>verification is complete.</div>+ /trunk/bench/verilog/altera_mf.v<br />+ /trunk/bench/verilog/host_sim.v<br />~ /trunk/bench/verilog/Phy_sim.v<br />~ /trunk/bench/verilog/tb_top.v<br />~ /trunk/bench/verilog/User_int_sim.v<br />~ /trunk/rtl/verilog/Clk_ctrl.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />+ /trunk/rtl/verilog/header.v<br />~ /trunk/rtl/verilog/MAC_rx.v<br />~ /trunk/rtl/verilog/MAC_rx/Broadcast_filter.v<br />~ /trunk/rtl/verilog/MAC_rx/CRC_chk.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />~ /trunk/rtl/verilog/MAC_top.v<br />~ /trunk/rtl/verilog/MAC_tx.v<br />~ /trunk/rtl/verilog/MAC_tx/CRC_gen.v<br />~ /trunk/rtl/verilog/MAC_tx/flow_ctrl.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v<br />~ /trunk/rtl/verilog/MAC_tx/Ramdon_gen.v<br />~ /trunk/rtl/verilog/Phy_int.v<br />+ /trunk/rtl/verilog/reg_int.v<br />~ /trunk/rtl/verilog/RMON.v<br />~ /trunk/rtl/verilog/RMON/RMON_addr_gen.v<br />~ /trunk/rtl/verilog/RMON/RMON_ctrl.v<br />~ /trunk/rtl/verilog/RMON/RMON_dpram.v<br />~ /trunk/rtl/verilog/TECH/CLK_DIV2.v<br />~ /trunk/rtl/verilog/TECH/CLK_SWITCH.v<br />~ /trunk/rtl/verilog/TECH/duram.v<br />~ /trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/com.nc<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll<br />~ /trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/sim_only.nc<br />~ /trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list<br />+ /trunk/sim/rtl_sim/ncsim_sim/data<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/46-50.ini<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/batch.dat<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/config.ini<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/CPU.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec<br />+ /trunk/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec<br />+ /trunk/start.tcl<br />~ /trunk/syn/syn.prj<br /> maverickist Thu, 19 Jan 2006 14:07:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=7 first simulation passed https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=6 <div><strong>Rev 6 - maverickist</strong> (45 file(s) modified)</div><div>first simulation passed</div>+ /trunk/bench/verilog/Phy_sim.v<br />+ /trunk/bench/verilog/reg_int_sim.v<br />~ /trunk/bench/verilog/tb_top.v<br />+ /trunk/bench/verilog/User_int_sim.v<br />~ /trunk/rtl/verilog/Clk_ctrl.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/MAC_rx.v<br />~ /trunk/rtl/verilog/MAC_rx/Broadcast_filter.v<br />~ /trunk/rtl/verilog/MAC_rx/CRC_chk.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v<br />~ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />~ /trunk/rtl/verilog/MAC_top.v<br />~ /trunk/rtl/verilog/MAC_tx.v<br />~ /trunk/rtl/verilog/MAC_tx/CRC_gen.v<br />~ /trunk/rtl/verilog/MAC_tx/flow_ctrl.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v<br />~ /trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v<br />~ /trunk/rtl/verilog/MAC_tx/Ramdon_gen.v<br />~ /trunk/rtl/verilog/miim/eth_clockgen.v<br />~ /trunk/rtl/verilog/miim/eth_outputcontrol.v<br />~ /trunk/rtl/verilog/miim/eth_shiftreg.v<br />~ /trunk/rtl/verilog/miim/timescale.v<br />~ /trunk/rtl/verilog/Phy_int.v<br />~ /trunk/rtl/verilog/RMON.v<br />~ /trunk/rtl/verilog/RMON/RMON_addr_gen.v<br />~ /trunk/rtl/verilog/RMON/RMON_ctrl.v<br />+ /trunk/rtl/verilog/TECH/afifo.v<br />~ /trunk/rtl/verilog/TECH/CLK_DIV2.v<br />~ /trunk/rtl/verilog/TECH/CLK_SWITCH.v<br />+ /trunk/rtl/verilog/TECH/duram.v<br />+ /trunk/sim<br />+ /trunk/sim/rtl_sim<br />+ /trunk/sim/rtl_sim/ncsim_sim<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/cds.lib<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/config.ini<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/hdl.var<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/sim.nc<br />+ /trunk/sim/rtl_sim/ncsim_sim/bin/vlog.list<br />+ /trunk/syn<br />+ /trunk/syn/syn.prj<br /> maverickist Tue, 13 Dec 2005 12:54:54 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=6 no message https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=5 <div><strong>Rev 5 - maverickist</strong> (37 file(s) modified)</div><div>no message</div>+ /trunk/bench<br />+ /trunk/bench/verilog<br />+ /trunk/bench/verilog/tb_top.v<br />+ /trunk/rtl<br />+ /trunk/rtl/verilog<br />+ /trunk/rtl/verilog/Clk_ctrl.v<br />+ /trunk/rtl/verilog/eth_miim.v<br />+ /trunk/rtl/verilog/MAC_rx<br />+ /trunk/rtl/verilog/MAC_rx.v<br />+ /trunk/rtl/verilog/MAC_rx/Broadcast_filter.v<br />+ /trunk/rtl/verilog/MAC_rx/CRC_chk.v<br />+ /trunk/rtl/verilog/MAC_rx/MAC_rx_add_chk.v<br />+ /trunk/rtl/verilog/MAC_rx/MAC_rx_ctrl.v<br />+ /trunk/rtl/verilog/MAC_rx/MAC_rx_FF.v<br />+ /trunk/rtl/verilog/MAC_top.v<br />+ /trunk/rtl/verilog/MAC_tx<br />+ /trunk/rtl/verilog/MAC_tx.v<br />+ /trunk/rtl/verilog/MAC_tx/CRC_gen.v<br />+ /trunk/rtl/verilog/MAC_tx/flow_ctrl.v<br />+ /trunk/rtl/verilog/MAC_tx/MAC_tx_addr_add.v<br />+ /trunk/rtl/verilog/MAC_tx/MAC_tx_Ctrl.v<br />+ /trunk/rtl/verilog/MAC_tx/MAC_tx_FF.v<br />+ /trunk/rtl/verilog/MAC_tx/Ramdon_gen.v<br />+ /trunk/rtl/verilog/miim<br />+ /trunk/rtl/verilog/miim/eth_clockgen.v<br />+ /trunk/rtl/verilog/miim/eth_outputcontrol.v<br />+ /trunk/rtl/verilog/miim/eth_shiftreg.v<br />+ /trunk/rtl/verilog/miim/timescale.v<br />+ /trunk/rtl/verilog/Phy_int.v<br />+ /trunk/rtl/verilog/RMON<br />+ /trunk/rtl/verilog/RMON.v<br />+ /trunk/rtl/verilog/RMON/RMON_addr_gen.v<br />+ /trunk/rtl/verilog/RMON/RMON_ctrl.v<br />+ /trunk/rtl/verilog/RMON/RMON_dpram.v<br />+ /trunk/rtl/verilog/TECH<br />+ /trunk/rtl/verilog/TECH/CLK_DIV2.v<br />+ /trunk/rtl/verilog/TECH/CLK_SWITCH.v<br /> maverickist Mon, 05 Dec 2005 10:55:39 +0100 https://opencores.org/websvn//websvn/revision?repname=ethernet_tri_mode&path=%2Fethernet_tri_mode%2Ftrunk%2Frtl%2Fverilog%2F&rev=5
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