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ethmac
WebSVN RSS feed - ethmac
https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2F&
Thu, 28 Mar 2024 13:00:56 +0100
FeedCreator 1.7.2
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added Makefiles to build project
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2F&rev=362
<div><strong>Rev 362 - unneback</strong> (2 file(s) modified)</div><div>added Makefiles to build project</div>+ /ethmac/branches/unneback/Makefile<br />+ /ethmac/branches/unneback/rtl/verilog/Makefile<br />
unneback
Tue, 09 Aug 2011 11:57:23 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2F&rev=362
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created branch unneback
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2F&rev=361
<div><strong>Rev 361 - unneback</strong> (1 file(s) modified)</div><div>created branch unneback</div>+ /ethmac/branches/unneback<br />
unneback
Tue, 09 Aug 2011 11:48:59 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2F&rev=361
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Removed delayed assignments from rtl code
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=352
<div><strong>Rev 352 - olof</strong> (24 file(s) modified)</div><div>Removed delayed assignments from rtl code</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Fri, 29 Jul 2011 10:25:44 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=352
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Turn defines into parameters in eth_cop
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=351
<div><strong>Rev 351 - olof</strong> (2 file(s) modified)</div><div>Turn defines into parameters in eth_cop</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:35:36 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=351
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Turn M[1-2]_ADDRESSED_S[1-2] defines into wires
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=350
<div><strong>Rev 350 - olof</strong> (2 file(s) modified)</div><div>Turn M[1-2]_ADDRESSED_S[1-2] defines into wires</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:00:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=350
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Make all parameters configurable from top level
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=349
<div><strong>Rev 349 - olof</strong> (6 file(s) modified)</div><div>Make all parameters configurable from top level</div>~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Tue, 19 Jul 2011 19:22:42 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=349
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Added option to dump VCD files
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=348
<div><strong>Rev 348 - olof</strong> (3 file(s) modified)</div><div>Added option to dump VCD files</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/README.txt<br />~ /ethmac/trunk/scripts/Makefile<br />
olof
Mon, 18 Jul 2011 20:23:38 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=348
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Added information about running with Icarus Verilog
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=347
<div><strong>Rev 347 - olof</strong> (1 file(s) modified)</div><div>Added information about running with Icarus Verilog</div>~ /ethmac/trunk/README.txt<br />
olof
Mon, 18 Jul 2011 19:45:58 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=347
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Updated project location
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=346
<div><strong>Rev 346 - olof</strong> (36 file(s) modified)</div><div>Updated project location</div>~ /ethmac/trunk/bench/verilog/eth_host.v<br />~ /ethmac/trunk/bench/verilog/eth_memory.v<br />~ /ethmac/trunk/bench/verilog/eth_phy.v<br />~ /ethmac/trunk/bench/verilog/eth_phy_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />~ /ethmac/trunk/bench/verilog/wb_master32.v<br />~ /ethmac/trunk/bench/verilog/wb_master_behavioral.v<br />~ /ethmac/trunk/bench/verilog/wb_model_defines.v<br />~ /ethmac/trunk/bench/verilog/wb_slave_behavioral.v<br />~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/rtl/verilog/timescale.v<br />
olof
Mon, 18 Jul 2011 17:38:57 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=346
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Temporarily disable failing tests
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=345
<div><strong>Rev 345 - olof</strong> (1 file(s) modified)</div><div>Temporarily disable failing tests</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />
olof
Mon, 18 Jul 2011 16:07:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=345
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bit 9 in phy control register is self clearing
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=344
<div><strong>Rev 344 - olof</strong> (1 file(s) modified)</div><div>bit 9 in phy control register is self clearing</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />
olof
Tue, 12 Jul 2011 14:02:12 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=344
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Address miss should not be asserted on short frames
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=343
<div><strong>Rev 343 - olof</strong> (1 file(s) modified)</div><div>Address miss should not be asserted on short frames</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />
olof
Fri, 08 Jul 2011 18:06:04 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=343
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Added cast to avoid inequality when comparing different data types
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=342
<div><strong>Rev 342 - olof</strong> (1 file(s) modified)</div><div>Added cast to avoid inequality when comparing different data types</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />
olof
Fri, 08 Jul 2011 17:58:55 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=342
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Reset AdressMiss signal on new frames to prevent reporting the ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=341
<div><strong>Rev 341 - olof</strong> (2 file(s) modified)</div><div>Reset AdressMiss signal on new frames to prevent reporting the ...</div>~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />
olof
Fri, 08 Jul 2011 17:44:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=341
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Don't fail if log dir already exists
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=340
<div><strong>Rev 340 - olof</strong> (1 file(s) modified)</div><div>Don't fail if log dir already exists</div>~ /ethmac/trunk/scripts/Makefile<br />
olof
Thu, 07 Jul 2011 20:20:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=340
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Added basic support for Icarus Verilog
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=339
<div><strong>Rev 339 - olof</strong> (3 file(s) modified)</div><div>Added basic support for Icarus Verilog</div>+ /ethmac/trunk/scripts<br />+ /ethmac/trunk/scripts/icarus.scr<br />+ /ethmac/trunk/scripts/Makefile<br />
olof
Wed, 06 Jul 2011 20:58:21 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=339
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...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />
root
Tue, 05 May 2009 15:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=338
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethernet%2Ftrunk%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 10:03:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethernet%2Ftrunk%2F&rev=335
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Minor fixes for Icarus simulator.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=334
<div><strong>Rev 334 - igorm</strong> (1 file(s) modified)</div><div>Minor fixes for Icarus simulator.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />
igorm
Tue, 22 Mar 2005 07:56:26 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=334
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Some small fixes + some troubles fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=333
<div><strong>Rev 333 - igorm</strong> (5 file(s) modified)</div><div>Some small fixes + some troubles fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
igorm
Mon, 21 Mar 2005 20:07:18 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=333
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