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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2Feth_cop.v& Fri, 27 Nov 2020 08:03:18 +0100 FeedCreator 1.7.2 created branch unneback https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 <div><strong>Rev 361 - unneback</strong> (1 file(s) modified)</div><div>created branch unneback</div>+ /ethmac/branches/unneback<br /> unneback Tue, 09 Aug 2011 11:48:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 Removed delayed assignments from rtl code https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=352 <div><strong>Rev 352 - olof</strong> (24 file(s) modified)</div><div>Removed delayed assignments from rtl code</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br /> olof Fri, 29 Jul 2011 10:25:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=352 Turn defines into parameters in eth_cop https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=351 <div><strong>Rev 351 - olof</strong> (2 file(s) modified)</div><div>Turn defines into parameters in eth_cop</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br /> olof Wed, 20 Jul 2011 20:35:36 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=351 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=350 <div><strong>Rev 350 - olof</strong> (2 file(s) modified)</div><div>Turn M[1-2]_ADDRESSED_S[1-2] defines into wires</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br /> olof Wed, 20 Jul 2011 20:00:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=350 Updated project location https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 <div><strong>Rev 346 - olof</strong> (36 file(s) modified)</div><div>Updated project location</div>~ /ethmac/trunk/bench/verilog/eth_host.v<br />~ /ethmac/trunk/bench/verilog/eth_memory.v<br />~ /ethmac/trunk/bench/verilog/eth_phy.v<br />~ /ethmac/trunk/bench/verilog/eth_phy_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />~ /ethmac/trunk/bench/verilog/wb_master32.v<br />~ /ethmac/trunk/bench/verilog/wb_master_behavioral.v<br />~ /ethmac/trunk/bench/verilog/wb_model_defines.v<br />~ /ethmac/trunk/bench/verilog/wb_slave_behavioral.v<br />~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/rtl/verilog/timescale.v<br /> olof Mon, 18 Jul 2011 17:38:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 Define file in eth_cop.v is changed to eth_defines.v. Some defines ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=286 <div><strong>Rev 286 - mohor</strong> (3 file(s) modified)</div><div>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 13 Jun 2003 11:55:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=286 Minor $display change. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=212 <div><strong>Rev 212 - mohor</strong> (1 file(s) modified)</div><div>Minor $display change.</div>~ /trunk/rtl/verilog/eth_cop.v<br /> mohor Thu, 10 Oct 2002 16:43:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=212 error acknowledge cycle termination added to display. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=160 <div><strong>Rev 160 - mohor</strong> (1 file(s) modified)</div><div>error acknowledge cycle termination added to display.</div>~ /trunk/rtl/verilog/eth_cop.v<br /> mohor Mon, 09 Sep 2002 12:54:13 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=160 Traffic cop with 2 wishbone master interfaces and 2 wishbona ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=129 <div><strong>Rev 129 - mohor</strong> (1 file(s) modified)</div><div>Traffic cop with 2 wishbone master interfaces and 2 wishbona ...</div>+ /trunk/rtl/verilog/eth_cop.v<br /> mohor Wed, 14 Aug 2002 17:16:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=129
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