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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2Feth_defines.v& Fri, 27 Nov 2020 09:31:43 +0100 FeedCreator 1.7.2 created branch unneback https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 <div><strong>Rev 361 - unneback</strong> (1 file(s) modified)</div><div>created branch unneback</div>+ /ethmac/branches/unneback<br /> unneback Tue, 09 Aug 2011 11:48:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 Turn defines into parameters in eth_cop https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=351 <div><strong>Rev 351 - olof</strong> (2 file(s) modified)</div><div>Turn defines into parameters in eth_cop</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br /> olof Wed, 20 Jul 2011 20:35:36 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=351 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=350 <div><strong>Rev 350 - olof</strong> (2 file(s) modified)</div><div>Turn M[1-2]_ADDRESSED_S[1-2] defines into wires</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br /> olof Wed, 20 Jul 2011 20:00:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=350 Updated project location https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 <div><strong>Rev 346 - olof</strong> (36 file(s) modified)</div><div>Updated project location</div>~ /ethmac/trunk/bench/verilog/eth_host.v<br />~ /ethmac/trunk/bench/verilog/eth_memory.v<br />~ /ethmac/trunk/bench/verilog/eth_phy.v<br />~ /ethmac/trunk/bench/verilog/eth_phy_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />~ /ethmac/trunk/bench/verilog/wb_master32.v<br />~ /ethmac/trunk/bench/verilog/wb_master_behavioral.v<br />~ /ethmac/trunk/bench/verilog/wb_model_defines.v<br />~ /ethmac/trunk/bench/verilog/wb_slave_behavioral.v<br />~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/rtl/verilog/timescale.v<br /> olof Mon, 18 Jul 2011 17:38:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 Warning fixes. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=330 <div><strong>Rev 330 - igorm</strong> (6 file(s) modified)</div><div>Warning fixes.</div>~ /trunk/rtl/verilog/eth_clockgen.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_fifo.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> igorm Mon, 21 Feb 2005 12:48:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=330 WISHBONE slave changed and tested from only 32-bit accesss to ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=304 <div><strong>Rev 304 - tadejm</strong> (5 file(s) modified)</div><div>WISHBONE slave changed and tested from only 32-bit accesss to ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 12 Nov 2003 18:24:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=304 mbist signals updated according to newest convention https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=302 <div><strong>Rev 302 - markom</strong> (6 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> markom Fri, 17 Oct 2003 07:46:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=302 Artisan ram instance added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=297 <div><strong>Rev 297 - simons</strong> (2 file(s) modified)</div><div>Artisan ram instance added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> simons Thu, 14 Aug 2003 16:42:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=297 Define file in eth_cop.v is changed to eth_defines.v. Some defines ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=286 <div><strong>Rev 286 - mohor</strong> (3 file(s) modified)</div><div>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 13 Jun 2003 11:55:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=286 r_MiiMRst is not used for resetting the MIIM module. wb_rst ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=253 <div><strong>Rev 253 - mohor</strong> (3 file(s) modified)</div><div>r_MiiMRst is not used for resetting the MIIM module. wb_rst ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Tue, 19 Nov 2002 18:13:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=253 Since r_Rst bit is not used any more, default value ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=246 <div><strong>Rev 246 - mohor</strong> (1 file(s) modified)</div><div>Since r_Rst bit is not used any more, default value ...</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 15 Nov 2002 14:27:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=246 Defines fixed to use generic RAM by default. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=238 <div><strong>Rev 238 - mohor</strong> (1 file(s) modified)</div><div>Defines fixed to use generic RAM by default.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 01 Nov 2002 18:19:34 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=238 fpga define added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=232 <div><strong>Rev 232 - mohor</strong> (1 file(s) modified)</div><div>fpga define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 24 Oct 2002 18:53:03 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=232 Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=213 <div><strong>Rev 213 - mohor</strong> (1 file(s) modified)</div><div>Defines changed to have ETH_ prolog.<br /> ETH_WISHBONE_B# define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:47:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=213 Bist added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=211 <div><strong>Rev 211 - mohor</strong> (1 file(s) modified)</div><div>Bist added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:33:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=211 Virtual Silicon RAM might be used in the ASIC implementation ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=203 <div><strong>Rev 203 - mohor</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM might be used in the ASIC implementation ...</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Mon, 23 Sep 2002 18:22:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=203 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=145 <div><strong>Rev 145 - mohor</strong> (1 file(s) modified)</div><div>Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Wed, 04 Sep 2002 18:36:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=145 Defines for register width added. mii_rst signal in MIIMODER register changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=137 <div><strong>Rev 137 - mohor</strong> (1 file(s) modified)</div><div>Defines for register width added. mii_rst signal in MIIMODER register<br /> changed.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 16 Aug 2002 22:09:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=137
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