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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2Feth_wishbone.v& Sun, 29 Nov 2020 07:56:44 +0100 FeedCreator 1.7.2 created branch unneback https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 <div><strong>Rev 361 - unneback</strong> (1 file(s) modified)</div><div>created branch unneback</div>+ /ethmac/branches/unneback<br /> unneback Tue, 09 Aug 2011 11:48:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=361 Removed delayed assignments from rtl code https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=352 <div><strong>Rev 352 - olof</strong> (24 file(s) modified)</div><div>Removed delayed assignments from rtl code</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br /> olof Fri, 29 Jul 2011 10:25:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=352 Make all parameters configurable from top level https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=349 <div><strong>Rev 349 - olof</strong> (6 file(s) modified)</div><div>Make all parameters configurable from top level</div>~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br /> olof Tue, 19 Jul 2011 19:22:42 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=349 Updated project location https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 <div><strong>Rev 346 - olof</strong> (36 file(s) modified)</div><div>Updated project location</div>~ /ethmac/trunk/bench/verilog/eth_host.v<br />~ /ethmac/trunk/bench/verilog/eth_memory.v<br />~ /ethmac/trunk/bench/verilog/eth_phy.v<br />~ /ethmac/trunk/bench/verilog/eth_phy_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />~ /ethmac/trunk/bench/verilog/wb_master32.v<br />~ /ethmac/trunk/bench/verilog/wb_master_behavioral.v<br />~ /ethmac/trunk/bench/verilog/wb_model_defines.v<br />~ /ethmac/trunk/bench/verilog/wb_slave_behavioral.v<br />~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/rtl/verilog/timescale.v<br /> olof Mon, 18 Jul 2011 17:38:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=346 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=335 Some small fixes + some troubles fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=333 <div><strong>Rev 333 - igorm</strong> (5 file(s) modified)</div><div>Some small fixes + some troubles fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 21 Mar 2005 20:07:18 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=333 Defer indication fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=329 <div><strong>Rev 329 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 21 Feb 2005 11:35:33 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=329 Accidently deleted line put back. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=323 <div><strong>Rev 323 - igorm</strong> (1 file(s) modified)</div><div>Accidently deleted line put back.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Fri, 30 Apr 2004 10:30:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=323 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=321 <div><strong>Rev 321 - igorm</strong> (4 file(s) modified)</div><div>- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 26 Apr 2004 15:26:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=321 WISHBONE slave changed and tested from only 32-bit accesss to ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=304 <div><strong>Rev 304 - tadejm</strong> (5 file(s) modified)</div><div>WISHBONE slave changed and tested from only 32-bit accesss to ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 12 Nov 2003 18:24:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=304 mbist signals updated according to newest convention https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=302 <div><strong>Rev 302 - markom</strong> (6 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> markom Fri, 17 Oct 2003 07:46:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=302 Reset has priority in some flipflops. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=280 <div><strong>Rev 280 - mohor</strong> (1 file(s) modified)</div><div>Reset has priority in some flipflops.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 14:51:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=280 A new bug (entered with previous update) fixed. When abort ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=278 <div><strong>Rev 278 - mohor</strong> (1 file(s) modified)</div><div>A new bug (entered with previous update) fixed. When abort ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 13:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=278 When control packets were received, they were ignored in some ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=272 <div><strong>Rev 272 - tadejm</strong> (4 file(s) modified)</div><div>When control packets were received, they were ignored in some ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 22 Jan 2003 13:49:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=272 When receiving normal data frame and RxFlow control was switched ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=270 <div><strong>Rev 270 - mohor</strong> (2 file(s) modified)</div><div>When receiving normal data frame and RxFlow control was switched ...</div>~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 21 Jan 2003 12:09:40 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=270 When in full duplex, transmit was sometimes blocked. Fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=269 <div><strong>Rev 269 - mohor</strong> (1 file(s) modified)</div><div>When in full duplex, transmit was sometimes blocked. Fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Mon, 20 Jan 2003 12:05:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=269 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=264 <div><strong>Rev 264 - mohor</strong> (1 file(s) modified)</div><div>Registers RxStatusWrite_rck and RxStatusWriteLatched were not used<br /> anywhere. Removed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 22 Nov 2002 13:26:21 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=264 Rx Flow control fixed. CF flag added to the RX ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=261 <div><strong>Rev 261 - mohor</strong> (8 file(s) modified)</div><div>Rx Flow control fixed. CF flag added to the RX ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 22 Nov 2002 01:57:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=261 AddressMiss status is connecting to the Rx BD. AddressMiss is ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=250 <div><strong>Rev 250 - mohor</strong> (4 file(s) modified)</div><div>AddressMiss status is connecting to the Rx BD. AddressMiss is ...</div>~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 19 Nov 2002 17:35:35 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Fbranches%2Funneback%2Frtl%2Fverilog%2F&rev=250
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