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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F& Sat, 14 Dec 2019 14:09:27 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'asyst_2'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=313 <div><strong>Rev 313 - </strong> (5 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'asyst_2'.</div>+ /tags/asyst_2<br />- /tags/asyst_2/bench<br />- /tags/asyst_2/doc<br />- /tags/asyst_2/README.txt<br />- /tags/asyst_2/sim<br /> Fri, 05 Dec 2003 12:43:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=313 Corrected address mismatch for xilinx RAMB4_S8 model which has wider ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=312 <div><strong>Rev 312 - tadejm</strong> (1 file(s) modified)</div><div>Corrected address mismatch for xilinx RAMB4_S8 model which has wider ...</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> tadejm Fri, 05 Dec 2003 12:43:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=312 Lapsus fixed (!we -&gt; ~we). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=306 <div><strong>Rev 306 - simons</strong> (1 file(s) modified)</div><div>Lapsus fixed (!we -&gt; ~we).</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> simons Thu, 04 Dec 2003 14:59:13 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=306 WISHBONE slave changed and tested from only 32-bit accesss to ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=304 <div><strong>Rev 304 - tadejm</strong> (5 file(s) modified)</div><div>WISHBONE slave changed and tested from only 32-bit accesss to ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 12 Nov 2003 18:24:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=304 mbist signals updated according to newest convention https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=302 <div><strong>Rev 302 - markom</strong> (6 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> markom Fri, 17 Oct 2003 07:46:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=302 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=301 <div><strong>Rev 301 - knguyen</strong> (1 file(s) modified)</div><div>Update RxEnSync only when mrxdv_pad_i is inactive (LOW).</div>~ /trunk/rtl/verilog/eth_top.v<br /> knguyen Mon, 06 Oct 2003 15:43:45 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=301 Artisan ram instance added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=297 <div><strong>Rev 297 - simons</strong> (2 file(s) modified)</div><div>Artisan ram instance added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> simons Thu, 14 Aug 2003 16:42:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=297 This file was not part of the RTL before, but ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=288 <div><strong>Rev 288 - simons</strong> (1 file(s) modified)</div><div>This file was not part of the RTL before, but ...</div>+ /trunk/rtl/verilog/xilinx_dist_ram_16x32.v<br /> simons Wed, 09 Jul 2003 14:53:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=288 Define file in eth_cop.v is changed to eth_defines.v. Some defines ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=286 <div><strong>Rev 286 - mohor</strong> (3 file(s) modified)</div><div>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 13 Jun 2003 11:55:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=286 Binary operator used instead of unary (xnor). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=285 <div><strong>Rev 285 - mohor</strong> (1 file(s) modified)</div><div>Binary operator used instead of unary (xnor).</div>~ /trunk/rtl/verilog/eth_random.v<br /> mohor Fri, 13 Jun 2003 11:26:08 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=285 Busy was set 2 cycles too late. Reported by Dennis ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=284 <div><strong>Rev 284 - mohor</strong> (1 file(s) modified)</div><div>Busy was set 2 cycles too late. Reported by Dennis ...</div>~ /trunk/rtl/verilog/eth_miim.v<br /> mohor Fri, 16 May 2003 10:08:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=284 RxBDAddress was updated also when value to r_TxBDNum was written ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=283 <div><strong>Rev 283 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress was updated also when value to r_TxBDNum was written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 18 Apr 2003 16:26:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=283 Reset has priority in some flipflops. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=280 <div><strong>Rev 280 - mohor</strong> (1 file(s) modified)</div><div>Reset has priority in some flipflops.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 14:51:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=280 A new bug (entered with previous update) fixed. When abort ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=278 <div><strong>Rev 278 - mohor</strong> (1 file(s) modified)</div><div>A new bug (entered with previous update) fixed. When abort ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 13:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=278 When padding was enabled and crc disabled, frame was not ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=277 <div><strong>Rev 277 - mohor</strong> (1 file(s) modified)</div><div>When padding was enabled and crc disabled, frame was not ...</div>~ /trunk/rtl/verilog/eth_txethmac.v<br /> mohor Thu, 30 Jan 2003 13:33:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=277 Defer indication changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=276 <div><strong>Rev 276 - tadejm</strong> (3 file(s) modified)</div><div>Defer indication changed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_txstatem.v<br /> tadejm Thu, 30 Jan 2003 13:30:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=276 Fix MTxErr or prevent sending too big frames. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=275 <div><strong>Rev 275 - mohor</strong> (1 file(s) modified)</div><div>Fix MTxErr or prevent sending too big frames.</div>~ /trunk/rtl/verilog/TODO<br /> mohor Thu, 23 Jan 2003 09:14:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=275 When control packets were received, they were ignored in some ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=272 <div><strong>Rev 272 - tadejm</strong> (4 file(s) modified)</div><div>When control packets were received, they were ignored in some ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 22 Jan 2003 13:49:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Fasyst_2%2Frtl%2F&rev=272
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