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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F& Sun, 17 Nov 2019 17:03:34 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_1'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=123 <div><strong>Rev 123 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_1'.</div>+ /tags/rel_1<br /> Tue, 23 Jul 2002 16:36:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=123 ethernet spram added. So far a generic ram and xilinx ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=122 <div><strong>Rev 122 - mohor</strong> (1 file(s) modified)</div><div>ethernet spram added. So far a generic ram and xilinx ...</div>+ /trunk/rtl/verilog/eth_spram_256x32.v<br /> mohor Tue, 23 Jul 2002 16:36:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=122 Unused files removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=120 <div><strong>Rev 120 - mohor</strong> (2 file(s) modified)</div><div>Unused files removed.</div>- /trunk/rtl/verilog/eth_sync_clk1_clk2.v<br />- /trunk/rtl/verilog/eth_wishbonedma.v<br /> mohor Tue, 23 Jul 2002 15:28:50 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=120 Ram , used for BDs changed from generic_spram to eth_spram_256x32. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=119 <div><strong>Rev 119 - mohor</strong> (2 file(s) modified)</div><div>Ram , used for BDs changed from generic_spram to eth_spram_256x32.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 23 Jul 2002 15:28:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=119 ShiftEnded synchronization changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=118 <div><strong>Rev 118 - mohor</strong> (1 file(s) modified)</div><div>ShiftEnded synchronization changed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Sat, 20 Jul 2002 00:41:32 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=118 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=115 <div><strong>Rev 115 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 18 Jul 2002 16:11:46 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=115 EXTERNAL_DMA removed. External DMA not supported. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=114 <div><strong>Rev 114 - mohor</strong> (1 file(s) modified)</div><div>EXTERNAL_DMA removed. External DMA not supported.</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Wed, 17 Jul 2002 18:51:50 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=114 RxPointer bug fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=113 <div><strong>Rev 113 - mohor</strong> (1 file(s) modified)</div><div>RxPointer bug fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 11 Jul 2002 02:53:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=113 Previous bug wasn't succesfully removed. Now fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=112 <div><strong>Rev 112 - mohor</strong> (1 file(s) modified)</div><div>Previous bug wasn't succesfully removed. Now fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 10 Jul 2002 13:12:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=112 Master state machine had a bug when switching from master ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=111 <div><strong>Rev 111 - mohor</strong> (1 file(s) modified)</div><div>Master state machine had a bug when switching from master ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 09 Jul 2002 23:53:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=111 m_wb_cyc_o signal released after every single transfer. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=110 <div><strong>Rev 110 - mohor</strong> (1 file(s) modified)</div><div>m_wb_cyc_o signal released after every single transfer.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 09 Jul 2002 20:44:41 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=110 Comment removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=109 <div><strong>Rev 109 - mohor</strong> (1 file(s) modified)</div><div>Comment removed.</div>~ /trunk/rtl/verilog/eth_outputcontrol.v<br /> mohor Tue, 09 Jul 2002 20:11:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=109 Outputs registered. Reset changed for eth_wishbone module. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=106 <div><strong>Rev 106 - mohor</strong> (3 file(s) modified)</div><div>Outputs registered. Reset changed for eth_wishbone module.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 03 May 2002 10:15:50 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=106 Compiler directives added. Tx and Rx fifo size incremented. A ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=105 <div><strong>Rev 105 - mohor</strong> (2 file(s) modified)</div><div>Compiler directives added. Tx and Rx fifo size incremented. A ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 24 Apr 2002 08:52:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=105 FCS should not be included in NibbleMinFl. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=104 <div><strong>Rev 104 - mohor</strong> (1 file(s) modified)</div><div>FCS should not be included in NibbleMinFl.</div>~ /trunk/rtl/verilog/eth_txcounters.v<br /> mohor Mon, 22 Apr 2002 14:54:14 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=104 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=103 <div><strong>Rev 103 - mohor</strong> (1 file(s) modified)</div><div>Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is<br /> selected in eth_defines.v</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Mon, 22 Apr 2002 14:15:42 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=103 Interrupts are visible in the ETH_INT_SOURCE regardless if they are ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=102 <div><strong>Rev 102 - mohor</strong> (1 file(s) modified)</div><div>Interrupts are visible in the ETH_INT_SOURCE regardless if they are ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Mon, 22 Apr 2002 14:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=102 Short frame and ReceivedLengthOK were not detected correctly. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=101 <div><strong>Rev 101 - mohor</strong> (1 file(s) modified)</div><div>Short frame and ReceivedLengthOK were not detected correctly.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br /> mohor Mon, 22 Apr 2002 13:51:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_1%2Frtl%2F&rev=101
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