OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Error creating feed file, please check write permissions.
ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2Feth_defines.v& Sun, 25 Oct 2020 16:58:20 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_14'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=271 <div><strong>Rev 271 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_14'.</div>+ /tags/rel_14<br /> Tue, 21 Jan 2003 12:09:41 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=271 r_MiiMRst is not used for resetting the MIIM module. wb_rst ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=253 <div><strong>Rev 253 - mohor</strong> (3 file(s) modified)</div><div>r_MiiMRst is not used for resetting the MIIM module. wb_rst ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Tue, 19 Nov 2002 18:13:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=253 Since r_Rst bit is not used any more, default value ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=246 <div><strong>Rev 246 - mohor</strong> (1 file(s) modified)</div><div>Since r_Rst bit is not used any more, default value ...</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 15 Nov 2002 14:27:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=246 Defines fixed to use generic RAM by default. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=238 <div><strong>Rev 238 - mohor</strong> (1 file(s) modified)</div><div>Defines fixed to use generic RAM by default.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 01 Nov 2002 18:19:34 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=238 fpga define added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=232 <div><strong>Rev 232 - mohor</strong> (1 file(s) modified)</div><div>fpga define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 24 Oct 2002 18:53:03 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=232 Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=213 <div><strong>Rev 213 - mohor</strong> (1 file(s) modified)</div><div>Defines changed to have ETH_ prolog.<br /> ETH_WISHBONE_B# define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:47:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=213 Bist added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=211 <div><strong>Rev 211 - mohor</strong> (1 file(s) modified)</div><div>Bist added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:33:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=211 Virtual Silicon RAM might be used in the ASIC implementation ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=203 <div><strong>Rev 203 - mohor</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM might be used in the ASIC implementation ...</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Mon, 23 Sep 2002 18:22:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=203 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=145 <div><strong>Rev 145 - mohor</strong> (1 file(s) modified)</div><div>Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Wed, 04 Sep 2002 18:36:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=145 Defines for register width added. mii_rst signal in MIIMODER register changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=137 <div><strong>Rev 137 - mohor</strong> (1 file(s) modified)</div><div>Defines for register width added. mii_rst signal in MIIMODER register<br /> changed.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 16 Aug 2002 22:09:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=137 Register TX_BD_NUM is changed so it contains value of the ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=134 <div><strong>Rev 134 - mohor</strong> (2 file(s) modified)</div><div>Register TX_BD_NUM is changed so it contains value of the ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 14 Aug 2002 19:31:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=134 Ram , used for BDs changed from generic_spram to eth_spram_256x32. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=119 <div><strong>Rev 119 - mohor</strong> (2 file(s) modified)</div><div>Ram , used for BDs changed from generic_spram to eth_spram_256x32.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 23 Jul 2002 15:28:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=119 Outputs registered. Reset changed for eth_wishbone module. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=106 <div><strong>Rev 106 - mohor</strong> (3 file(s) modified)</div><div>Outputs registered. Reset changed for eth_wishbone module.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 03 May 2002 10:15:50 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=106 Compiler directives added. Tx and Rx fifo size incremented. A ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=105 <div><strong>Rev 105 - mohor</strong> (2 file(s) modified)</div><div>Compiler directives added. Tx and Rx fifo size incremented. A ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 24 Apr 2002 08:52:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=105 Some defines that are used in testbench only were moved ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=92 <div><strong>Rev 92 - mohor</strong> (2 file(s) modified)</div><div>Some defines that are used in testbench only were moved ...</div>+ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Tue, 19 Mar 2002 12:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=92 Number of interrupts changed https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=73 <div><strong>Rev 73 - mohor</strong> (1 file(s) modified)</div><div>Number of interrupts changed</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Tue, 26 Feb 2002 16:11:32 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=73 Registered trimmed. Unused registers removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=68 <div><strong>Rev 68 - mohor</strong> (3 file(s) modified)</div><div>Registered trimmed. Unused registers removed.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Sat, 16 Feb 2002 14:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=68 EXTERNAL_DMA used instead of WISHBONE_DMA. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=67 <div><strong>Rev 67 - mohor</strong> (3 file(s) modified)</div><div>EXTERNAL_DMA used instead of WISHBONE_DMA.</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Sat, 16 Feb 2002 13:06:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_14%2Frtl%2Fverilog%2F&rev=67
© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.