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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F& Mon, 16 Sep 2019 08:14:04 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_16'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=282 <div><strong>Rev 282 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_16'.</div>+ /tags/rel_16<br /> Fri, 31 Jan 2003 15:58:28 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=282 Reset has priority in some flipflops. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=280 <div><strong>Rev 280 - mohor</strong> (1 file(s) modified)</div><div>Reset has priority in some flipflops.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 14:51:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=280 A new bug (entered with previous update) fixed. When abort ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=278 <div><strong>Rev 278 - mohor</strong> (1 file(s) modified)</div><div>A new bug (entered with previous update) fixed. When abort ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 13:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=278 When padding was enabled and crc disabled, frame was not ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=277 <div><strong>Rev 277 - mohor</strong> (1 file(s) modified)</div><div>When padding was enabled and crc disabled, frame was not ...</div>~ /trunk/rtl/verilog/eth_txethmac.v<br /> mohor Thu, 30 Jan 2003 13:33:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=277 Defer indication changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=276 <div><strong>Rev 276 - tadejm</strong> (3 file(s) modified)</div><div>Defer indication changed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_txstatem.v<br /> tadejm Thu, 30 Jan 2003 13:30:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=276 Fix MTxErr or prevent sending too big frames. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=275 <div><strong>Rev 275 - mohor</strong> (1 file(s) modified)</div><div>Fix MTxErr or prevent sending too big frames.</div>~ /trunk/rtl/verilog/TODO<br /> mohor Thu, 23 Jan 2003 09:14:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=275 When control packets were received, they were ignored in some ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=272 <div><strong>Rev 272 - tadejm</strong> (4 file(s) modified)</div><div>When control packets were received, they were ignored in some ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 22 Jan 2003 13:49:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=272 When receiving normal data frame and RxFlow control was switched ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=270 <div><strong>Rev 270 - mohor</strong> (2 file(s) modified)</div><div>When receiving normal data frame and RxFlow control was switched ...</div>~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 21 Jan 2003 12:09:40 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=270 When in full duplex, transmit was sometimes blocked. Fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=269 <div><strong>Rev 269 - mohor</strong> (1 file(s) modified)</div><div>When in full duplex, transmit was sometimes blocked. Fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Mon, 20 Jan 2003 12:05:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=269 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=264 <div><strong>Rev 264 - mohor</strong> (1 file(s) modified)</div><div>Registers RxStatusWrite_rck and RxStatusWriteLatched were not used<br /> anywhere. Removed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 22 Nov 2002 13:26:21 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=264 Rx Flow control fixed. CF flag added to the RX ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=261 <div><strong>Rev 261 - mohor</strong> (8 file(s) modified)</div><div>Rx Flow control fixed. CF flag added to the RX ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 22 Nov 2002 01:57:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=261 In loopback rx_clk is not looped back. Possible CRC error. ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=259 <div><strong>Rev 259 - mohor</strong> (1 file(s) modified)</div><div>In loopback rx_clk is not looped back. Possible CRC error. ...</div>~ /trunk/rtl/verilog/TODO<br /> mohor Thu, 21 Nov 2002 00:33:32 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=259 When TxUsedData and CtrlMux occur at the same time, byte ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=257 <div><strong>Rev 257 - mohor</strong> (1 file(s) modified)</div><div>When TxUsedData and CtrlMux occur at the same time, byte ...</div>~ /trunk/rtl/verilog/eth_transmitcontrol.v<br /> mohor Thu, 21 Nov 2002 00:16:14 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=257 TxDone and TxAbort changed so they're not propagated to the ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=256 <div><strong>Rev 256 - mohor</strong> (1 file(s) modified)</div><div>TxDone and TxAbort changed so they're not propagated to the ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br /> mohor Thu, 21 Nov 2002 00:14:39 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=256 TPauseRq synchronized to tx_clk. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=255 <div><strong>Rev 255 - mohor</strong> (1 file(s) modified)</div><div>TPauseRq synchronized to tx_clk.</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Thu, 21 Nov 2002 00:09:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=255 r_MiiMRst is not used for resetting the MIIM module. wb_rst ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=253 <div><strong>Rev 253 - mohor</strong> (3 file(s) modified)</div><div>r_MiiMRst is not used for resetting the MIIM module. wb_rst ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Tue, 19 Nov 2002 18:13:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=253 When control frame (PAUSE) was sent, status was written in ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=251 <div><strong>Rev 251 - mohor</strong> (2 file(s) modified)</div><div>When control frame (PAUSE) was sent, status was written in ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_transmitcontrol.v<br /> mohor Tue, 19 Nov 2002 17:37:32 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=251 AddressMiss status is connecting to the Rx BD. AddressMiss is ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=250 <div><strong>Rev 250 - mohor</strong> (4 file(s) modified)</div><div>AddressMiss status is connecting to the Rx BD. AddressMiss is ...</div>~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 19 Nov 2002 17:35:35 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_16%2Frtl%2F&rev=250
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