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            <description>&lt;div&gt;&lt;strong&gt;Rev 338 - root&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;...&lt;/div&gt;- /ethernet&lt;br /&gt;+ /ethmac&lt;br /&gt;</description>
            <author>root</author>
            <pubDate>Tue, 05 May 2009 15:18:25 +0100</pubDate>
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            <title>New directory structure.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=335</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 335 - root&lt;/strong&gt; (8 file(s) modified)&lt;/div&gt;&lt;div&gt;New directory structure.&lt;/div&gt;- /branches&lt;br /&gt;+ /ethernet&lt;br /&gt;+ /ethernet/branches&lt;br /&gt;+ /ethernet/tags&lt;br /&gt;+ /ethernet/trunk&lt;br /&gt;+ /ethernet/web_uploads&lt;br /&gt;- /tags&lt;br /&gt;- /trunk&lt;br /&gt;</description>
            <author>root</author>
            <pubDate>Mon, 09 Mar 2009 10:03:10 +0100</pubDate>
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            <title>This commit was manufactured by cvs2svn to create tag 'rel_17'.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=287</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 287 - &lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;This commit was manufactured by cvs2svn to create tag 'rel_17'.&lt;/div&gt;+ /tags/rel_17&lt;br /&gt;</description>
            <pubDate>Fri, 13 Jun 2003 11:55:38 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=287</guid>
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            <title>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=286</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 286 - mohor&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Define file in eth_cop.v is changed to eth_defines.v. Some defines ...&lt;/div&gt;~ /trunk/bench/verilog/tb_eth_defines.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_cop.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_defines.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Fri, 13 Jun 2003 11:55:37 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=286</guid>
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        <item>
            <title>Binary operator used instead of unary (xnor).</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=285</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 285 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Binary operator used instead of unary (xnor).&lt;/div&gt;~ /trunk/rtl/verilog/eth_random.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Fri, 13 Jun 2003 11:26:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=285</guid>
        </item>
        <item>
            <title>Busy was set 2 cycles too late. Reported by Dennis ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=284</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 284 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Busy was set 2 cycles too late. Reported by Dennis ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_miim.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Fri, 16 May 2003 10:08:27 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=284</guid>
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        <item>
            <title>RxBDAddress was updated also when value to r_TxBDNum was written ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=283</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 283 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;RxBDAddress was updated also when value to r_TxBDNum was written ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_registers.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Fri, 18 Apr 2003 16:26:25 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=283</guid>
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        <item>
            <title>Tests test_mac_full_duplex_receive 4-7  fixed to proper BD.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=281</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 281 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Tests test_mac_full_duplex_receive 4-7  fixed to proper BD.&lt;/div&gt;~ /trunk/bench/verilog/tb_ethernet.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Fri, 31 Jan 2003 15:58:27 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=281</guid>
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        <item>
            <title>Reset has priority in some flipflops.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=280</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 280 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Reset has priority in some flipflops.&lt;/div&gt;~ /trunk/rtl/verilog/eth_wishbone.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Thu, 30 Jan 2003 14:51:31 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=280</guid>
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            <title>Underrun test fixed. Many other tests fixed.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=279</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 279 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Underrun test fixed. Many other tests fixed.&lt;/div&gt;~ /trunk/bench/verilog/tb_ethernet.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Thu, 30 Jan 2003 13:38:15 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=279</guid>
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            <title>A new bug (entered with previous update) fixed. When abort ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=278</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 278 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;A new bug (entered with previous update) fixed. When abort ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_wishbone.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Thu, 30 Jan 2003 13:36:22 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=278</guid>
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        <item>
            <title>When padding was enabled and crc disabled, frame was not ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=277</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 277 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;When padding was enabled and crc disabled, frame was not ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_txethmac.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Thu, 30 Jan 2003 13:33:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=277</guid>
        </item>
        <item>
            <title>Defer indication changed.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=276</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 276 - tadejm&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Defer indication changed.&lt;/div&gt;~ /trunk/rtl/verilog/eth_macstatus.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_top.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_txstatem.v&lt;br /&gt;</description>
            <author>tadejm</author>
            <pubDate>Thu, 30 Jan 2003 13:30:22 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=276</guid>
        </item>
        <item>
            <title>Fix MTxErr or prevent sending too big frames.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=275</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 275 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fix MTxErr or prevent sending too big frames.&lt;/div&gt;~ /trunk/rtl/verilog/TODO&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Thu, 23 Jan 2003 09:14:12 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=275</guid>
        </item>
        <item>
            <title>Backup version. Not fully working.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=274</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 274 - tadejm&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Backup version. Not fully working.&lt;/div&gt;~ /trunk/bench/verilog/eth_phy.v&lt;br /&gt;~ /trunk/bench/verilog/tb_ethernet.v&lt;br /&gt;</description>
            <author>tadejm</author>
            <pubDate>Wed, 22 Jan 2003 19:40:10 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=274</guid>
        </item>
        <item>
            <title>When control packets were received, they were ignored in some ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=272</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 272 - tadejm&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;When control packets were received, they were ignored in some ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_maccontrol.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_receivecontrol.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_top.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_wishbone.v&lt;br /&gt;</description>
            <author>tadejm</author>
            <pubDate>Wed, 22 Jan 2003 13:49:26 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=272</guid>
        </item>
        <item>
            <title>When receiving normal data frame and RxFlow control was switched ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=270</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 270 - mohor&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;When receiving normal data frame and RxFlow control was switched ...&lt;/div&gt;~ /trunk/rtl/verilog/eth_top.v&lt;br /&gt;~ /trunk/rtl/verilog/eth_wishbone.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Tue, 21 Jan 2003 12:09:40 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=270</guid>
        </item>
        <item>
            <title>When in full duplex, transmit was sometimes blocked. Fixed.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=269</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 269 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;When in full duplex, transmit was sometimes blocked. Fixed.&lt;/div&gt;~ /trunk/rtl/verilog/eth_wishbone.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Mon, 20 Jan 2003 12:05:26 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=269</guid>
        </item>
        <item>
            <title>Release 1.19. Control frame description changed.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=268</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 268 - mohor&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Release 1.19. Control frame description changed.&lt;/div&gt;~ /trunk/doc/eth_speci.pdf&lt;br /&gt;~ /trunk/doc/src/eth_speci.doc&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Wed, 27 Nov 2002 18:46:16 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=268</guid>
        </item>
        <item>
            <title>Full duplex control frames tested.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=267</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 267 - mohor&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Full duplex control frames tested.&lt;/div&gt;~ /trunk/bench/verilog/tb_ethernet.v&lt;br /&gt;</description>
            <author>mohor</author>
            <pubDate>Wed, 27 Nov 2002 16:21:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=ethmac&amp;path=%2Fethmac%2Ftags%2Frel_17%2F&amp;rev=267</guid>
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