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ethmac
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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&
Fri, 29 Mar 2024 04:50:05 +0100
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https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />
root
Tue, 05 May 2009 15:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=338
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 10:03:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=335
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This commit was manufactured by cvs2svn to create tag 'rel_2'.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=128
<div><strong>Rev 128 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_2'.</div>+ /tags/rel_2<br />
Thu, 25 Jul 2002 18:29:02 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=128
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WriteRxDataToMemory signal changed so end of frame (when last word ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=127
<div><strong>Rev 127 - mohor</strong> (1 file(s) modified)</div><div>WriteRxDataToMemory signal changed so end of frame (when last word ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Thu, 25 Jul 2002 18:29:01 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=127
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InvalidSymbol generation changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=126
<div><strong>Rev 126 - mohor</strong> (1 file(s) modified)</div><div>InvalidSymbol generation changed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />
mohor
Thu, 25 Jul 2002 18:17:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=126
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RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=125
<div><strong>Rev 125 - mohor</strong> (1 file(s) modified)</div><div>RxAbort changed. Packets received with MRxErr (from PHY) are also<br />
aborted.</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Thu, 25 Jul 2002 18:15:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=125
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Define ETH_MIIMODER_RST corrected to 0x00000400.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=124
<div><strong>Rev 124 - mohor</strong> (1 file(s) modified)</div><div>Define ETH_MIIMODER_RST corrected to 0x00000400.</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />
mohor
Thu, 25 Jul 2002 17:19:06 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=124
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ethernet spram added. So far a generic ram and xilinx ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=122
<div><strong>Rev 122 - mohor</strong> (1 file(s) modified)</div><div>ethernet spram added. So far a generic ram and xilinx ...</div>+ /trunk/rtl/verilog/eth_spram_256x32.v<br />
mohor
Tue, 23 Jul 2002 16:36:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=122
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gsr added for use when ETH_XILINX_RAMB4 define is set.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=121
<div><strong>Rev 121 - mohor</strong> (1 file(s) modified)</div><div>gsr added for use when ETH_XILINX_RAMB4 define is set.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />
mohor
Tue, 23 Jul 2002 16:34:31 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=121
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Unused files removed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=120
<div><strong>Rev 120 - mohor</strong> (2 file(s) modified)</div><div>Unused files removed.</div>- /trunk/rtl/verilog/eth_sync_clk1_clk2.v<br />- /trunk/rtl/verilog/eth_wishbonedma.v<br />
mohor
Tue, 23 Jul 2002 15:28:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=120
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Ram , used for BDs changed from generic_spram to eth_spram_256x32.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=119
<div><strong>Rev 119 - mohor</strong> (2 file(s) modified)</div><div>Ram , used for BDs changed from generic_spram to eth_spram_256x32.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Tue, 23 Jul 2002 15:28:31 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=119
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ShiftEnded synchronization changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=118
<div><strong>Rev 118 - mohor</strong> (1 file(s) modified)</div><div>ShiftEnded synchronization changed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Sat, 20 Jul 2002 00:41:32 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=118
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Clock mrx_clk set to 2.5 MHz.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=117
<div><strong>Rev 117 - mohor</strong> (1 file(s) modified)</div><div>Clock mrx_clk set to 2.5 MHz.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />
mohor
Fri, 19 Jul 2002 14:02:47 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=117
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Testing environment also includes traffic cop, memory interface and host
interface.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=116
<div><strong>Rev 116 - mohor</strong> (5 file(s) modified)</div><div>Testing environment also includes traffic cop, memory interface and host<br />
interface.</div>+ /trunk/bench/verilog/eth_host.v<br />+ /trunk/bench/verilog/eth_memory.v<br />+ /trunk/bench/verilog/tb_cop.v<br />+ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_eth_defines.v<br />
mohor
Fri, 19 Jul 2002 13:57:53 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=116
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RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=115
<div><strong>Rev 115 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Thu, 18 Jul 2002 16:11:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=115
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EXTERNAL_DMA removed. External DMA not supported.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=114
<div><strong>Rev 114 - mohor</strong> (1 file(s) modified)</div><div>EXTERNAL_DMA removed. External DMA not supported.</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Wed, 17 Jul 2002 18:51:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=114
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RxPointer bug fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=113
<div><strong>Rev 113 - mohor</strong> (1 file(s) modified)</div><div>RxPointer bug fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Thu, 11 Jul 2002 02:53:20 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=113
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Previous bug wasn't succesfully removed. Now fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=112
<div><strong>Rev 112 - mohor</strong> (1 file(s) modified)</div><div>Previous bug wasn't succesfully removed. Now fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Wed, 10 Jul 2002 13:12:38 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=112
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Master state machine had a bug when switching from master ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=111
<div><strong>Rev 111 - mohor</strong> (1 file(s) modified)</div><div>Master state machine had a bug when switching from master ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Tue, 09 Jul 2002 23:53:24 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=111
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m_wb_cyc_o signal released after every single transfer.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=110
<div><strong>Rev 110 - mohor</strong> (1 file(s) modified)</div><div>m_wb_cyc_o signal released after every single transfer.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Tue, 09 Jul 2002 20:44:41 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_2%2F&rev=110
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