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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F& Mon, 16 Sep 2019 12:13:34 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_20'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=298 <div><strong>Rev 298 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_20'.</div>+ /tags/rel_20<br /> Thu, 14 Aug 2003 16:42:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=298 Artisan ram instance added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=297 <div><strong>Rev 297 - simons</strong> (2 file(s) modified)</div><div>Artisan ram instance added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> simons Thu, 14 Aug 2003 16:42:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=297 Few minor changes. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=295 <div><strong>Rev 295 - tadejm</strong> (1 file(s) modified)</div><div>Few minor changes.</div>~ /trunk/sim/rtl_sim/ncsim_sim/run/run_eth_sim_regr.scr<br /> tadejm Wed, 13 Aug 2003 13:41:56 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=295 Added path to a file with distributed RAM instances for ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=294 <div><strong>Rev 294 - tadejm</strong> (1 file(s) modified)</div><div>Added path to a file with distributed RAM instances for ...</div>~ /trunk/sim/rtl_sim/bin/rtl_file_list.lst<br /> tadejm Mon, 11 Aug 2003 13:17:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=294 initial. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=293 <div><strong>Rev 293 - tadejm</strong> (2 file(s) modified)</div><div>initial.</div>+ /trunk/sim/rtl_sim/bin/ncelab.args<br />+ /trunk/sim/rtl_sim/bin/ncelab_xilinx.args<br /> tadejm Fri, 18 Jul 2003 16:14:02 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=293 Corrected mistake. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=292 <div><strong>Rev 292 - tadejm</strong> (1 file(s) modified)</div><div>Corrected mistake.</div>~ /trunk/sim/rtl_sim/run/run_eth_sim_regr.scr<br /> tadejm Fri, 18 Jul 2003 16:12:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=292 initial https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=291 <div><strong>Rev 291 - tadejm</strong> (21 file(s) modified)</div><div>initial</div>+ /trunk/sim/rtl_sim/bin<br />+ /trunk/sim/rtl_sim/bin/artisan_file_list.lst<br />+ /trunk/sim/rtl_sim/bin/cds.lib<br />+ /trunk/sim/rtl_sim/bin/hdl.var<br />+ /trunk/sim/rtl_sim/bin/INCA_libs<br />+ /trunk/sim/rtl_sim/bin/INCA_libs/worklib<br />+ /trunk/sim/rtl_sim/bin/INCA_libs/worklib/dir_keeper<br />+ /trunk/sim/rtl_sim/bin/ncsim.rc<br />+ /trunk/sim/rtl_sim/bin/ncsim_waves.rc<br />+ /trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />+ /trunk/sim/rtl_sim/bin/run_sim<br />+ /trunk/sim/rtl_sim/bin/sim_file_list.lst<br />+ /trunk/sim/rtl_sim/bin/xilinx_file_list.lst<br />+ /trunk/sim/rtl_sim/log<br />+ /trunk/sim/rtl_sim/log/dir_keeper<br />+ /trunk/sim/rtl_sim/out<br />+ /trunk/sim/rtl_sim/out/dir_keeper<br />+ /trunk/sim/rtl_sim/run<br />+ /trunk/sim/rtl_sim/run/clean<br />+ /trunk/sim/rtl_sim/run/run_eth_sim_regr.scr<br />+ /trunk/sim/rtl_sim/run/top_groups.do<br /> tadejm Fri, 18 Jul 2003 14:47:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=291 Additional checking for FAILED tests added - for ATS. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=290 <div><strong>Rev 290 - tadejm</strong> (1 file(s) modified)</div><div>Additional checking for FAILED tests added - for ATS.</div>~ /trunk/sim/rtl_sim/ncsim_sim/run/run_eth_sim_regr.scr<br /> tadejm Fri, 18 Jul 2003 13:51:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=290 This file was not part of the RTL before, but ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=288 <div><strong>Rev 288 - simons</strong> (1 file(s) modified)</div><div>This file was not part of the RTL before, but ...</div>+ /trunk/rtl/verilog/xilinx_dist_ram_16x32.v<br /> simons Wed, 09 Jul 2003 14:53:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=288 Define file in eth_cop.v is changed to eth_defines.v. Some defines ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=286 <div><strong>Rev 286 - mohor</strong> (3 file(s) modified)</div><div>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 13 Jun 2003 11:55:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=286 Binary operator used instead of unary (xnor). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=285 <div><strong>Rev 285 - mohor</strong> (1 file(s) modified)</div><div>Binary operator used instead of unary (xnor).</div>~ /trunk/rtl/verilog/eth_random.v<br /> mohor Fri, 13 Jun 2003 11:26:08 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=285 Busy was set 2 cycles too late. Reported by Dennis ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=284 <div><strong>Rev 284 - mohor</strong> (1 file(s) modified)</div><div>Busy was set 2 cycles too late. Reported by Dennis ...</div>~ /trunk/rtl/verilog/eth_miim.v<br /> mohor Fri, 16 May 2003 10:08:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=284 RxBDAddress was updated also when value to r_TxBDNum was written ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=283 <div><strong>Rev 283 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress was updated also when value to r_TxBDNum was written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 18 Apr 2003 16:26:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=283 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=281 <div><strong>Rev 281 - mohor</strong> (1 file(s) modified)</div><div>Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> mohor Fri, 31 Jan 2003 15:58:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=281 Reset has priority in some flipflops. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=280 <div><strong>Rev 280 - mohor</strong> (1 file(s) modified)</div><div>Reset has priority in some flipflops.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 14:51:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=280 Underrun test fixed. Many other tests fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=279 <div><strong>Rev 279 - mohor</strong> (1 file(s) modified)</div><div>Underrun test fixed. Many other tests fixed.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> mohor Thu, 30 Jan 2003 13:38:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=279 A new bug (entered with previous update) fixed. When abort ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=278 <div><strong>Rev 278 - mohor</strong> (1 file(s) modified)</div><div>A new bug (entered with previous update) fixed. When abort ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 30 Jan 2003 13:36:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=278 When padding was enabled and crc disabled, frame was not ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=277 <div><strong>Rev 277 - mohor</strong> (1 file(s) modified)</div><div>When padding was enabled and crc disabled, frame was not ...</div>~ /trunk/rtl/verilog/eth_txethmac.v<br /> mohor Thu, 30 Jan 2003 13:33:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_20%2F&rev=277
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