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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&
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https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />rootTue, 05 May 2009 15:18:25 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=338New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />rootMon, 09 Mar 2009 10:03:10 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=335This commit was manufactured by cvs2svn to create tag 'rel_24'.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=307
<div><strong>Rev 307 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_24'.</div>+ /tags/rel_24<br />Thu, 04 Dec 2003 14:59:14 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=307Lapsus fixed (!we -> ~we).
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=306
<div><strong>Rev 306 - simons</strong> (1 file(s) modified)</div><div>Lapsus fixed (!we -> ~we).</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br />simonsThu, 04 Dec 2003 14:59:13 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=306WISHBONE slave changed and tested from only 32-bit accesss to ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=304
<div><strong>Rev 304 - tadejm</strong> (5 file(s) modified)</div><div>WISHBONE slave changed and tested from only 32-bit accesss to ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />tadejmWed, 12 Nov 2003 18:24:59 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=304mbist signals updated according to newest convention
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=302
<div><strong>Rev 302 - markom</strong> (6 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />markomFri, 17 Oct 2003 07:46:17 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=302Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=301
<div><strong>Rev 301 - knguyen</strong> (1 file(s) modified)</div><div>Update RxEnSync only when mrxdv_pad_i is inactive (LOW).</div>~ /trunk/rtl/verilog/eth_top.v<br />knguyenMon, 06 Oct 2003 15:43:45 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=301Artisan ram instance added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=297
<div><strong>Rev 297 - simons</strong> (2 file(s) modified)</div><div>Artisan ram instance added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />simonsThu, 14 Aug 2003 16:42:58 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=297This file was not part of the RTL before, but ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=288
<div><strong>Rev 288 - simons</strong> (1 file(s) modified)</div><div>This file was not part of the RTL before, but ...</div>+ /trunk/rtl/verilog/xilinx_dist_ram_16x32.v<br />simonsWed, 09 Jul 2003 14:53:07 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=288Define file in eth_cop.v is changed to eth_defines.v. Some defines ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=286
<div><strong>Rev 286 - mohor</strong> (3 file(s) modified)</div><div>Define file in eth_cop.v is changed to eth_defines.v. Some defines ...</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />mohorFri, 13 Jun 2003 11:55:37 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=286Binary operator used instead of unary (xnor).
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=285
<div><strong>Rev 285 - mohor</strong> (1 file(s) modified)</div><div>Binary operator used instead of unary (xnor).</div>~ /trunk/rtl/verilog/eth_random.v<br />mohorFri, 13 Jun 2003 11:26:08 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=285Busy was set 2 cycles too late. Reported by Dennis ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=284
<div><strong>Rev 284 - mohor</strong> (1 file(s) modified)</div><div>Busy was set 2 cycles too late. Reported by Dennis ...</div>~ /trunk/rtl/verilog/eth_miim.v<br />mohorFri, 16 May 2003 10:08:27 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=284RxBDAddress was updated also when value to r_TxBDNum was written ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=283
<div><strong>Rev 283 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress was updated also when value to r_TxBDNum was written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />mohorFri, 18 Apr 2003 16:26:25 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=283Reset has priority in some flipflops.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=280
<div><strong>Rev 280 - mohor</strong> (1 file(s) modified)</div><div>Reset has priority in some flipflops.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />mohorThu, 30 Jan 2003 14:51:31 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=280A new bug (entered with previous update) fixed. When abort ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=278
<div><strong>Rev 278 - mohor</strong> (1 file(s) modified)</div><div>A new bug (entered with previous update) fixed. When abort ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />mohorThu, 30 Jan 2003 13:36:22 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=278When padding was enabled and crc disabled, frame was not ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=277
<div><strong>Rev 277 - mohor</strong> (1 file(s) modified)</div><div>When padding was enabled and crc disabled, frame was not ...</div>~ /trunk/rtl/verilog/eth_txethmac.v<br />mohorThu, 30 Jan 2003 13:33:24 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=277Defer indication changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=276
<div><strong>Rev 276 - tadejm</strong> (3 file(s) modified)</div><div>Defer indication changed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_txstatem.v<br />tadejmThu, 30 Jan 2003 13:30:22 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=276Fix MTxErr or prevent sending too big frames.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=275
<div><strong>Rev 275 - mohor</strong> (1 file(s) modified)</div><div>Fix MTxErr or prevent sending too big frames.</div>~ /trunk/rtl/verilog/TODO<br />mohorThu, 23 Jan 2003 09:14:12 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=275When control packets were received, they were ignored in some ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=272
<div><strong>Rev 272 - tadejm</strong> (4 file(s) modified)</div><div>When control packets were received, they were ignored in some ...</div>~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />tadejmWed, 22 Jan 2003 13:49:26 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=272When receiving normal data frame and RxFlow control was switched ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=270
<div><strong>Rev 270 - mohor</strong> (2 file(s) modified)</div><div>When receiving normal data frame and RxFlow control was switched ...</div>~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />mohorTue, 21 Jan 2003 12:09:40 +0100https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_24%2Frtl%2Fverilog%2F&rev=270