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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F& Thu, 05 Mar 2026 13:22:00 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_27'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=324 <div><strong>Rev 324 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_27'.</div>+ /tags/rel_27<br /> Fri, 30 Apr 2004 10:30:01 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=324 Accidently deleted line put back. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=323 <div><strong>Rev 323 - igorm</strong> (1 file(s) modified)</div><div>Accidently deleted line put back.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Fri, 30 Apr 2004 10:30:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=323 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=321 <div><strong>Rev 321 - igorm</strong> (4 file(s) modified)</div><div>- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 26 Apr 2004 15:26:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=321 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=320 <div><strong>Rev 320 - igorm</strong> (1 file(s) modified)</div><div>TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> igorm Mon, 26 Apr 2004 11:42:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=320 Latest Ethernet IP core testbench. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=319 <div><strong>Rev 319 - tadejm</strong> (4 file(s) modified)</div><div>Latest Ethernet IP core testbench.</div>+ /trunk/sim/rtl_sim/ncsim_sim/log/eth_tb.log<br />+ /trunk/sim/rtl_sim/ncsim_sim/log/tb_eth_display.log<br />~ /trunk/sim/rtl_sim/ncsim_sim/run/run_eth_sim_regr.scr<br />~ /trunk/sim/rtl_sim/ncsim_sim/run/top_groups.do<br /> tadejm Fri, 26 Mar 2004 16:07:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=319 Latest Ethernet IP core testbench. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=318 <div><strong>Rev 318 - tadejm</strong> (2 file(s) modified)</div><div>Latest Ethernet IP core testbench.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/wb_slave_behavioral.v<br /> tadejm Fri, 26 Mar 2004 15:59:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=318 Multicast detection fixed. Only the LSB of the first byte ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=317 <div><strong>Rev 317 - igorm</strong> (1 file(s) modified)</div><div>Multicast detection fixed. Only the LSB of the first byte ...</div>~ /trunk/rtl/verilog/eth_rxethmac.v<br /> igorm Wed, 17 Mar 2004 09:32:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=317 Updated testbench. Some more testcases, some repaired. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=315 <div><strong>Rev 315 - tadejm</strong> (3 file(s) modified)</div><div>Updated testbench. Some more testcases, some repaired.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/wb_bus_mon.v<br />~ /trunk/bench/verilog/wb_model_defines.v<br /> tadejm Fri, 05 Dec 2003 12:46:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=315 Corrected address mismatch for xilinx RAMB4_S8 model which has wider ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=312 <div><strong>Rev 312 - tadejm</strong> (1 file(s) modified)</div><div>Corrected address mismatch for xilinx RAMB4_S8 model which has wider ...</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> tadejm Fri, 05 Dec 2003 12:43:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=312 Update script for running different file list files for different ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=311 <div><strong>Rev 311 - tadejm</strong> (1 file(s) modified)</div><div>Update script for running different file list files for different ...</div>~ /trunk/sim/rtl_sim/ncsim_sim/run/run_eth_sim_regr.scr<br /> tadejm Fri, 05 Dec 2003 12:40:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=311 More signals. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=310 <div><strong>Rev 310 - tadejm</strong> (1 file(s) modified)</div><div>More signals.</div>~ /trunk/sim/rtl_sim/ncsim_sim/run/top_groups.do<br /> tadejm Fri, 05 Dec 2003 12:38:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=310 Update file list files for different RAM models with byte ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=309 <div><strong>Rev 309 - tadejm</strong> (3 file(s) modified)</div><div>Update file list files for different RAM models with byte ...</div>~ /trunk/sim/rtl_sim/ncsim_sim/bin/artisan_file_list.lst<br />~ /trunk/sim/rtl_sim/ncsim_sim/bin/sim_file_list.lst<br />~ /trunk/sim/rtl_sim/ncsim_sim/bin/xilinx_file_list.lst<br /> tadejm Fri, 05 Dec 2003 12:37:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=309 Moved RAM model file path from sim_file_list.lst to this file. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=308 <div><strong>Rev 308 - tadejm</strong> (1 file(s) modified)</div><div>Moved RAM model file path from sim_file_list.lst to this file.</div>+ /trunk/sim/rtl_sim/ncsim_sim/bin/vs_file_list.lst<br /> tadejm Fri, 05 Dec 2003 12:36:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=308 Lapsus fixed (!we -&gt; ~we). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=306 <div><strong>Rev 306 - simons</strong> (1 file(s) modified)</div><div>Lapsus fixed (!we -&gt; ~we).</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> simons Thu, 04 Dec 2003 14:59:13 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=306 WISHBONE slave changed and tested from only 32-bit accesss to ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=304 <div><strong>Rev 304 - tadejm</strong> (5 file(s) modified)</div><div>WISHBONE slave changed and tested from only 32-bit accesss to ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Wed, 12 Nov 2003 18:24:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=304 mbist signals updated according to newest convention https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=302 <div><strong>Rev 302 - markom</strong> (6 file(s) modified)</div><div>mbist signals updated according to newest convention</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> markom Fri, 17 Oct 2003 07:46:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=302 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=301 <div><strong>Rev 301 - knguyen</strong> (1 file(s) modified)</div><div>Update RxEnSync only when mrxdv_pad_i is inactive (LOW).</div>~ /trunk/rtl/verilog/eth_top.v<br /> knguyen Mon, 06 Oct 2003 15:43:45 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=301 Artisan RAMs added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=299 <div><strong>Rev 299 - mohor</strong> (3 file(s) modified)</div><div>Artisan RAMs added.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/sim/rtl_sim/bin/sim_file_list.lst<br /> mohor Wed, 20 Aug 2003 12:12:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_27%2F&rev=299
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