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ethmac
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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&
Thu, 28 Mar 2024 12:33:57 +0100
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https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />
root
Tue, 05 May 2009 15:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=338
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 10:03:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=335
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This commit was manufactured by cvs2svn to create tag 'rel_3'.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=142
<div><strong>Rev 142 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_3'.</div>+ /tags/rel_3<br />
Fri, 16 Aug 2002 22:28:24 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=142
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Syntax error fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=141
<div><strong>Rev 141 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />
mohor
Fri, 16 Aug 2002 22:28:23 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=141
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Syntax error fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=140
<div><strong>Rev 140 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />
mohor
Fri, 16 Aug 2002 22:23:03 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=140
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Synchronous reset added to all registers. Defines used for width. ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=139
<div><strong>Rev 139 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added to all registers. Defines used for width. ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />
mohor
Fri, 16 Aug 2002 22:14:22 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=139
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Synchronous reset added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=138
<div><strong>Rev 138 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added.</div>~ /trunk/rtl/verilog/eth_register.v<br />
mohor
Fri, 16 Aug 2002 22:10:12 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=138
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Defines for register width added. mii_rst signal in MIIMODER register
changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=137
<div><strong>Rev 137 - mohor</strong> (1 file(s) modified)</div><div>Defines for register width added. mii_rst signal in MIIMODER register<br />
changed.</div>~ /trunk/rtl/verilog/eth_defines.v<br />
mohor
Fri, 16 Aug 2002 22:09:47 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=137
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Parameter ResetValue changed to capital letters.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=136
<div><strong>Rev 136 - mohor</strong> (1 file(s) modified)</div><div>Parameter ResetValue changed to capital letters.</div>~ /trunk/rtl/verilog/eth_register.v<br />
mohor
Fri, 16 Aug 2002 12:33:27 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=136
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New revision. External DMA removed, TX_BD_NUM changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=135
<div><strong>Rev 135 - mohor</strong> (2 file(s) modified)</div><div>New revision. External DMA removed, TX_BD_NUM changed.</div>~ /trunk/doc/eth_speci.pdf<br />~ /trunk/doc/src/eth_speci.doc<br />
mohor
Wed, 14 Aug 2002 20:41:57 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=135
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Register TX_BD_NUM is changed so it contains value of the ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=134
<div><strong>Rev 134 - mohor</strong> (2 file(s) modified)</div><div>Register TX_BD_NUM is changed so it contains value of the ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Wed, 14 Aug 2002 19:31:48 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=134
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- Busy signal was not set on time when scan ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=133
<div><strong>Rev 133 - mohor</strong> (1 file(s) modified)</div><div>- Busy signal was not set on time when scan ...</div>~ /trunk/rtl/verilog/eth_miim.v<br />
mohor
Wed, 14 Aug 2002 18:32:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=133
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LinkFailRegister is reflecting the status of the PHY's link fail ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=132
<div><strong>Rev 132 - mohor</strong> (1 file(s) modified)</div><div>LinkFailRegister is reflecting the status of the PHY's link fail ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />
mohor
Wed, 14 Aug 2002 18:26:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=132
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LinkFail signal was not latching appropriate bit.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=131
<div><strong>Rev 131 - mohor</strong> (1 file(s) modified)</div><div>LinkFail signal was not latching appropriate bit.</div>~ /trunk/rtl/verilog/eth_shiftreg.v<br />
mohor
Wed, 14 Aug 2002 18:16:59 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=131
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First draft of the Ethernet design document. Not a finished ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=130
<div><strong>Rev 130 - mohor</strong> (1 file(s) modified)</div><div>First draft of the Ethernet design document. Not a finished ...</div>+ /trunk/doc/src/eth_design_document.doc<br />
mohor
Wed, 14 Aug 2002 17:56:33 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=130
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Traffic cop with 2 wishbone master interfaces and 2 wishbona ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=129
<div><strong>Rev 129 - mohor</strong> (1 file(s) modified)</div><div>Traffic cop with 2 wishbone master interfaces and 2 wishbona ...</div>+ /trunk/rtl/verilog/eth_cop.v<br />
mohor
Wed, 14 Aug 2002 17:16:07 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=129
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WriteRxDataToMemory signal changed so end of frame (when last word ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=127
<div><strong>Rev 127 - mohor</strong> (1 file(s) modified)</div><div>WriteRxDataToMemory signal changed so end of frame (when last word ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Thu, 25 Jul 2002 18:29:01 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=127
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InvalidSymbol generation changed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=126
<div><strong>Rev 126 - mohor</strong> (1 file(s) modified)</div><div>InvalidSymbol generation changed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />
mohor
Thu, 25 Jul 2002 18:17:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=126
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RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=125
<div><strong>Rev 125 - mohor</strong> (1 file(s) modified)</div><div>RxAbort changed. Packets received with MRxErr (from PHY) are also<br />
aborted.</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Thu, 25 Jul 2002 18:15:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=125
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Define ETH_MIIMODER_RST corrected to 0x00000400.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=124
<div><strong>Rev 124 - mohor</strong> (1 file(s) modified)</div><div>Define ETH_MIIMODER_RST corrected to 0x00000400.</div>~ /trunk/bench/verilog/tb_eth_defines.v<br />
mohor
Thu, 25 Jul 2002 17:19:06 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_3%2F&rev=124
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