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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F& Mon, 21 Oct 2019 08:29:09 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_4'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=151 <div><strong>Rev 151 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_4'.</div>+ /tags/rel_4<br /> Wed, 04 Sep 2002 18:47:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=151 Debug registers reg1, 2, 3, 4 connected. Synchronization of many ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=150 <div><strong>Rev 150 - mohor</strong> (1 file(s) modified)</div><div>Debug registers reg1, 2, 3, 4 connected. Synchronization of many ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 04 Sep 2002 18:47:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=150 Signals related to the control frames connected. Debug registers reg1, ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=149 <div><strong>Rev 149 - mohor</strong> (1 file(s) modified)</div><div>Signals related to the control frames connected. Debug registers reg1, ...</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Wed, 04 Sep 2002 18:44:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=149 Bug when last byte of destination address was not checked ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=148 <div><strong>Rev 148 - mohor</strong> (1 file(s) modified)</div><div>Bug when last byte of destination address was not checked ...</div>~ /trunk/rtl/verilog/eth_rxaddrcheck.v<br /> mohor Wed, 04 Sep 2002 18:41:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=148 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=147 <div><strong>Rev 147 - mohor</strong> (1 file(s) modified)</div><div>ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to<br /> the control frames ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Wed, 04 Sep 2002 18:40:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=147 CarrierSenseLost status is not set when working in loopback mode. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=146 <div><strong>Rev 146 - mohor</strong> (1 file(s) modified)</div><div>CarrierSenseLost status is not set when working in loopback mode.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br /> mohor Wed, 04 Sep 2002 18:38:03 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=146 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=145 <div><strong>Rev 145 - mohor</strong> (1 file(s) modified)</div><div>Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Wed, 04 Sep 2002 18:36:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=145 Only values smaller or equal to 0x80 can be written ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=143 <div><strong>Rev 143 - mohor</strong> (1 file(s) modified)</div><div>Only values smaller or equal to 0x80 can be written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Mon, 19 Aug 2002 16:01:40 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=143 Syntax error fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=141 <div><strong>Rev 141 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:28:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=141 Syntax error fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=140 <div><strong>Rev 140 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:23:03 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=140 Synchronous reset added to all registers. Defines used for width. ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=139 <div><strong>Rev 139 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added to all registers. Defines used for width. ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:14:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=139 Synchronous reset added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=138 <div><strong>Rev 138 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added.</div>~ /trunk/rtl/verilog/eth_register.v<br /> mohor Fri, 16 Aug 2002 22:10:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=138 Defines for register width added. mii_rst signal in MIIMODER register changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=137 <div><strong>Rev 137 - mohor</strong> (1 file(s) modified)</div><div>Defines for register width added. mii_rst signal in MIIMODER register<br /> changed.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Fri, 16 Aug 2002 22:09:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=137 Parameter ResetValue changed to capital letters. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=136 <div><strong>Rev 136 - mohor</strong> (1 file(s) modified)</div><div>Parameter ResetValue changed to capital letters.</div>~ /trunk/rtl/verilog/eth_register.v<br /> mohor Fri, 16 Aug 2002 12:33:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=136 New revision. External DMA removed, TX_BD_NUM changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=135 <div><strong>Rev 135 - mohor</strong> (2 file(s) modified)</div><div>New revision. External DMA removed, TX_BD_NUM changed.</div>~ /trunk/doc/eth_speci.pdf<br />~ /trunk/doc/src/eth_speci.doc<br /> mohor Wed, 14 Aug 2002 20:41:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=135 Register TX_BD_NUM is changed so it contains value of the ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=134 <div><strong>Rev 134 - mohor</strong> (2 file(s) modified)</div><div>Register TX_BD_NUM is changed so it contains value of the ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 14 Aug 2002 19:31:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=134 - Busy signal was not set on time when scan ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=133 <div><strong>Rev 133 - mohor</strong> (1 file(s) modified)</div><div>- Busy signal was not set on time when scan ...</div>~ /trunk/rtl/verilog/eth_miim.v<br /> mohor Wed, 14 Aug 2002 18:32:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=133 LinkFailRegister is reflecting the status of the PHY's link fail ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=132 <div><strong>Rev 132 - mohor</strong> (1 file(s) modified)</div><div>LinkFailRegister is reflecting the status of the PHY's link fail ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Wed, 14 Aug 2002 18:26:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2F&rev=132
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