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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F& Tue, 19 Nov 2019 17:26:36 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_4'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=151 <div><strong>Rev 151 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_4'.</div>+ /tags/rel_4<br /> Wed, 04 Sep 2002 18:47:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=151 Define ETH_MIIMODER_RST corrected to 0x00000400. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=124 <div><strong>Rev 124 - mohor</strong> (1 file(s) modified)</div><div>Define ETH_MIIMODER_RST corrected to 0x00000400.</div>~ /trunk/bench/verilog/tb_eth_defines.v<br /> mohor Thu, 25 Jul 2002 17:19:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=124 gsr added for use when ETH_XILINX_RAMB4 define is set. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=121 <div><strong>Rev 121 - mohor</strong> (1 file(s) modified)</div><div>gsr added for use when ETH_XILINX_RAMB4 define is set.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> mohor Tue, 23 Jul 2002 16:34:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=121 Clock mrx_clk set to 2.5 MHz. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=117 <div><strong>Rev 117 - mohor</strong> (1 file(s) modified)</div><div>Clock mrx_clk set to 2.5 MHz.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> mohor Fri, 19 Jul 2002 14:02:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=117 Testing environment also includes traffic cop, memory interface and host interface. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=116 <div><strong>Rev 116 - mohor</strong> (5 file(s) modified)</div><div>Testing environment also includes traffic cop, memory interface and host<br /> interface.</div>+ /trunk/bench/verilog/eth_host.v<br />+ /trunk/bench/verilog/eth_memory.v<br />+ /trunk/bench/verilog/tb_cop.v<br />+ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_eth_defines.v<br /> mohor Fri, 19 Jul 2002 13:57:53 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=116 Testbench supports unaligned accesses. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=108 <div><strong>Rev 108 - mohor</strong> (1 file(s) modified)</div><div>Testbench supports unaligned accesses.</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> mohor Fri, 03 May 2002 10:25:01 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=108 TX_BUF_BASE changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=107 <div><strong>Rev 107 - mohor</strong> (1 file(s) modified)</div><div>TX_BUF_BASE changed.</div>~ /trunk/bench/verilog/tb_eth_defines.v<br /> mohor Fri, 03 May 2002 10:22:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=107 Some defines that are used in testbench only were moved ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=92 <div><strong>Rev 92 - mohor</strong> (2 file(s) modified)</div><div>Some defines that are used in testbench only were moved ...</div>+ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Tue, 19 Mar 2002 12:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=92 Small fixes for external/internal DMA missmatches. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=80 <div><strong>Rev 80 - mohor</strong> (4 file(s) modified)</div><div>Small fixes for external/internal DMA missmatches.</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br /> mohor Tue, 26 Feb 2002 17:01:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=80 EXTERNAL_DMA used instead of WISHBONE_DMA. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=67 <div><strong>Rev 67 - mohor</strong> (3 file(s) modified)</div><div>EXTERNAL_DMA used instead of WISHBONE_DMA.</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Sat, 16 Feb 2002 13:06:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=67 Testbench fixed, code simplified, unused signals removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=66 <div><strong>Rev 66 - mohor</strong> (1 file(s) modified)</div><div>Testbench fixed, code simplified, unused signals removed.</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> mohor Sat, 16 Feb 2002 07:22:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=66 Added separate tests for Multicast, Unicast, Broadcast https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=51 <div><strong>Rev 51 - billditt</strong> (1 file(s) modified)</div><div>Added separate tests for Multicast, Unicast, Broadcast</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> billditt Thu, 14 Feb 2002 20:14:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=51 HASH0 and HASH1 register read/write added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=49 <div><strong>Rev 49 - mohor</strong> (1 file(s) modified)</div><div>HASH0 and HASH1 register read/write added.</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> mohor Tue, 12 Feb 2002 20:24:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=49 non-DMA host interface added. Select the right configutation in eth_defines. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=41 <div><strong>Rev 41 - mohor</strong> (4 file(s) modified)</div><div>non-DMA host interface added. Select the right configutation in eth_defines.</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br /> mohor Wed, 06 Feb 2002 14:11:35 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=41 TX_BD_NUM register added instead of the RB_BD_ADDR. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=36 <div><strong>Rev 36 - mohor</strong> (1 file(s) modified)</div><div>TX_BD_NUM register added instead of the RB_BD_ADDR.</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> mohor Sat, 08 Dec 2001 12:36:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=36 Number of addresses (wb_adr_i) minimized. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=23 <div><strong>Rev 23 - mohor</strong> (3 file(s) modified)</div><div>Number of addresses (wb_adr_i) minimized.</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br /> mohor Fri, 19 Oct 2001 11:24:29 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=23 eth_timescale.v changed to timescale.v This is done because of the simulation ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=22 <div><strong>Rev 22 - mohor</strong> (24 file(s) modified)</div><div>eth_timescale.v changed to timescale.v This is done because of the<br /> simulation ...</div>~ /trunk/bench/verilog/tb_eth_top.v<br />~ /trunk/rtl/verilog/eth_clockgen.v<br />~ /trunk/rtl/verilog/eth_crc.v<br />~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_outputcontrol.v<br />~ /trunk/rtl/verilog/eth_random.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_register.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxcounters.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_rxstatem.v<br />~ /trunk/rtl/verilog/eth_shiftreg.v<br />~ /trunk/rtl/verilog/eth_sync_clk1_clk2.v<br />- /trunk/rtl/verilog/eth_timescale.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /trunk/rtl/verilog/eth_txcounters.v<br />~ /trunk/rtl/verilog/eth_txethmac.v<br />~ /trunk/rtl/verilog/eth_txstatem.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br />+ /trunk/rtl/verilog/timescale.v<br /> mohor Fri, 19 Oct 2001 08:46:53 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=22 Defines changed (All precede with ETH_). Small changes because some tools ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=19 <div><strong>Rev 19 - mohor</strong> (1 file(s) modified)</div><div>Defines changed (All precede with ETH_). Small changes because some<br /> tools ...</div>~ /trunk/bench/verilog/tb_eth_top.v<br /> mohor Mon, 24 Sep 2001 14:55:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_4%2Fbench%2F&rev=19
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