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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F& Thu, 21 Nov 2019 18:11:58 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_5'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=220 <div><strong>Rev 220 - </strong> (5 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_5'.</div>+ /tags/rel_5<br />- /tags/rel_5/bench<br />- /tags/rel_5/doc<br />- /tags/rel_5/README.txt<br />- /tags/rel_5/sim<br /> Fri, 11 Oct 2002 15:35:21 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=220 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=219 <div><strong>Rev 219 - mohor</strong> (1 file(s) modified)</div><div>txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 11 Oct 2002 15:35:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=219 Typo error fixed. (When using Bist) https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=218 <div><strong>Rev 218 - mohor</strong> (1 file(s) modified)</div><div>Typo error fixed. (When using Bist)</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Fri, 11 Oct 2002 13:36:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=218 Bist supported. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=217 <div><strong>Rev 217 - mohor</strong> (1 file(s) modified)</div><div>Bist supported.</div>~ /trunk/sim/rtl_sim/modelsim_sim/run/tb_eth.do<br /> mohor Fri, 11 Oct 2002 13:33:56 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=217 Bist signals added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=216 <div><strong>Rev 216 - mohor</strong> (1 file(s) modified)</div><div>Bist signals added.</div>~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br /> mohor Fri, 11 Oct 2002 13:29:28 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=216 Bist supported. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=215 <div><strong>Rev 215 - mohor</strong> (1 file(s) modified)</div><div>Bist supported.</div>~ /trunk/sim/rtl_sim/modelsim_sim/run/tb_eth.do<br /> mohor Fri, 11 Oct 2002 12:42:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=215 Signals for WISHBONE B3 compliant interface added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=214 <div><strong>Rev 214 - mohor</strong> (1 file(s) modified)</div><div>Signals for WISHBONE B3 compliant interface added.</div>~ /trunk/rtl/verilog/eth_top.v<br /> mohor Thu, 10 Oct 2002 16:49:50 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=214 Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=213 <div><strong>Rev 213 - mohor</strong> (1 file(s) modified)</div><div>Defines changed to have ETH_ prolog.<br /> ETH_WISHBONE_B# define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:47:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=213 Minor $display change. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=212 <div><strong>Rev 212 - mohor</strong> (1 file(s) modified)</div><div>Minor $display change.</div>~ /trunk/rtl/verilog/eth_cop.v<br /> mohor Thu, 10 Oct 2002 16:43:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=212 Bist added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=211 <div><strong>Rev 211 - mohor</strong> (1 file(s) modified)</div><div>Bist added.</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Thu, 10 Oct 2002 16:33:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=211 BIST added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=210 <div><strong>Rev 210 - mohor</strong> (3 file(s) modified)</div><div>BIST added.</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 10 Oct 2002 16:29:30 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=210 Just back-up; not completed testbench and some testcases are not wotking ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=209 <div><strong>Rev 209 - tadejm</strong> (4 file(s) modified)</div><div>Just back-up; not completed testbench and some testcases are not<br /> wotking ...</div>~ /trunk/bench/verilog/eth_phy.v<br />~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_eth_defines.v<br />~ /trunk/bench/verilog/wb_bus_mon.v<br /> tadejm Wed, 09 Oct 2002 13:16:51 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=209 Virtual Silicon RAMs moved to lib directory https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=208 <div><strong>Rev 208 - tadej</strong> (1 file(s) modified)</div><div>Virtual Silicon RAMs moved to lib directory</div>~ /trunk/sim/rtl_sim/ncsim_sim/bin/sim_file_list.lst<br /> tadej Mon, 23 Sep 2002 19:24:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=208 Virtual Silicon RAM support fixed https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=207 <div><strong>Rev 207 - tadej</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM support fixed</div>~ /trunk/sim/rtl_sim/ncsim_sim/bin/sim_file_list.lst<br /> tadej Mon, 23 Sep 2002 19:13:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=207 Virtual Silicon RAM added to the simulation. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=206 <div><strong>Rev 206 - mohor</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM added to the simulation.</div>~ /trunk/sim/rtl_sim/ncsim_sim/bin/sim_file_list.lst<br /> mohor Mon, 23 Sep 2002 19:05:35 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=206 ETH_VIRTUAL_SILICON_RAM supported. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=205 <div><strong>Rev 205 - mohor</strong> (1 file(s) modified)</div><div>ETH_VIRTUAL_SILICON_RAM supported.</div>~ /trunk/sim/rtl_sim/modelsim_sim/run/tb_eth.do<br /> mohor Mon, 23 Sep 2002 18:27:36 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=205 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=204 <div><strong>Rev 204 - mohor</strong> (1 file(s) modified)</div><div>ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> mohor Mon, 23 Sep 2002 18:24:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=204 Virtual Silicon RAM might be used in the ASIC implementation ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=203 <div><strong>Rev 203 - mohor</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM might be used in the ASIC implementation ...</div>~ /trunk/rtl/verilog/eth_defines.v<br /> mohor Mon, 23 Sep 2002 18:22:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_5%2F&rev=203
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