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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2Feth_registers.v& Thu, 06 Oct 2022 08:39:00 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_7'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=228 <div><strong>Rev 228 - </strong> (5 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_7'.</div>+ /tags/rel_7<br />- /tags/rel_7/bench<br />- /tags/rel_7/doc<br />- /tags/rel_7/README.txt<br />- /tags/rel_7/sim<br /> Fri, 18 Oct 2002 17:04:21 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=228 Ethernet debug registers removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=164 <div><strong>Rev 164 - mohor</strong> (3 file(s) modified)</div><div>Ethernet debug registers removed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 10 Sep 2002 10:35:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=164 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to the control frames ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=147 <div><strong>Rev 147 - mohor</strong> (1 file(s) modified)</div><div>ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to<br /> the control frames ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Wed, 04 Sep 2002 18:40:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=147 Only values smaller or equal to 0x80 can be written ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=143 <div><strong>Rev 143 - mohor</strong> (1 file(s) modified)</div><div>Only values smaller or equal to 0x80 can be written ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Mon, 19 Aug 2002 16:01:40 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=143 Syntax error fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=141 <div><strong>Rev 141 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:28:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=141 Syntax error fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=140 <div><strong>Rev 140 - mohor</strong> (1 file(s) modified)</div><div>Syntax error fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:23:03 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=140 Synchronous reset added to all registers. Defines used for width. ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=139 <div><strong>Rev 139 - mohor</strong> (1 file(s) modified)</div><div>Synchronous reset added to all registers. Defines used for width. ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 16 Aug 2002 22:14:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=139 LinkFailRegister is reflecting the status of the PHY's link fail ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=132 <div><strong>Rev 132 - mohor</strong> (1 file(s) modified)</div><div>LinkFailRegister is reflecting the status of the PHY's link fail ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Wed, 14 Aug 2002 18:26:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=132 Interrupts are visible in the ETH_INT_SOURCE regardless if they are ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=102 <div><strong>Rev 102 - mohor</strong> (1 file(s) modified)</div><div>Interrupts are visible in the ETH_INT_SOURCE regardless if they are ...</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Mon, 22 Apr 2002 14:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=102 Reset values are passed to registers through parameters https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=74 <div><strong>Rev 74 - mohor</strong> (2 file(s) modified)</div><div>Reset values are passed to registers through parameters</div>~ /trunk/rtl/verilog/eth_register.v<br />~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Tue, 26 Feb 2002 16:18:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=74 Define missmatch fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=69 <div><strong>Rev 69 - mohor</strong> (1 file(s) modified)</div><div>Define missmatch fixed.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Sun, 17 Feb 2002 13:23:42 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=69 Registered trimmed. Unused registers removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=68 <div><strong>Rev 68 - mohor</strong> (3 file(s) modified)</div><div>Registered trimmed. Unused registers removed.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> mohor Sat, 16 Feb 2002 14:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=68 File format fixed a bit. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=56 <div><strong>Rev 56 - mohor</strong> (1 file(s) modified)</div><div>File format fixed a bit.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Fri, 15 Feb 2002 11:08:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=56 Modified for Address Checking, addition of eth_addrcheck.v https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=52 <div><strong>Rev 52 - billditt</strong> (4 file(s) modified)</div><div>Modified for Address Checking,<br /> addition of eth_addrcheck.v</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxcounters.v<br />~ /trunk/rtl/verilog/eth_top.v<br /> billditt Thu, 14 Feb 2002 20:19:41 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=52 HASH0 and HASH1 registers added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=46 <div><strong>Rev 46 - mohor</strong> (2 file(s) modified)</div><div>HASH0 and HASH1 registers added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Tue, 12 Feb 2002 17:01:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=46 Link in the header changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=37 <div><strong>Rev 37 - mohor</strong> (23 file(s) modified)</div><div>Link in the header changed.</div>~ /trunk/rtl/verilog/eth_clockgen.v<br />~ /trunk/rtl/verilog/eth_crc.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_maccontrol.v<br />~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_outputcontrol.v<br />~ /trunk/rtl/verilog/eth_random.v<br />~ /trunk/rtl/verilog/eth_receivecontrol.v<br />~ /trunk/rtl/verilog/eth_register.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxcounters.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_rxstatem.v<br />~ /trunk/rtl/verilog/eth_shiftreg.v<br />~ /trunk/rtl/verilog/eth_sync_clk1_clk2.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /trunk/rtl/verilog/eth_txcounters.v<br />~ /trunk/rtl/verilog/eth_txethmac.v<br />~ /trunk/rtl/verilog/eth_txstatem.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br />~ /trunk/rtl/verilog/timescale.v<br /> mohor Wed, 23 Jan 2002 10:28:16 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=37 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=34 <div><strong>Rev 34 - mohor</strong> (4 file(s) modified)</div><div>RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors<br /> instead of ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbonedma.v<br /> mohor Wed, 05 Dec 2001 15:00:16 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=34 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=32 <div><strong>Rev 32 - mohor</strong> (2 file(s) modified)</div><div>ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_registers.v<br /> mohor Wed, 05 Dec 2001 10:22:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=32
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