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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2Feth_wishbone.v& Sat, 01 Oct 2022 02:30:49 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=335 This commit was manufactured by cvs2svn to create tag 'rel_7'. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=228 <div><strong>Rev 228 - </strong> (5 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_7'.</div>+ /tags/rel_7<br />- /tags/rel_7/bench<br />- /tags/rel_7/doc<br />- /tags/rel_7/README.txt<br />- /tags/rel_7/sim<br /> Fri, 18 Oct 2002 17:04:21 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=228 Changed BIST scan signals. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=227 <div><strong>Rev 227 - tadejm</strong> (5 file(s) modified)</div><div>Changed BIST scan signals.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Fri, 18 Oct 2002 17:04:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=227 Igor added WB burst support and repaired BUG when handling ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=226 <div><strong>Rev 226 - tadejm</strong> (1 file(s) modified)</div><div>Igor added WB burst support and repaired BUG when handling ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> tadejm Fri, 18 Oct 2002 15:42:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=226 TxStatus is written after last access to the TX fifo ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=221 <div><strong>Rev 221 - mohor</strong> (1 file(s) modified)</div><div>TxStatus is written after last access to the TX fifo ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Mon, 14 Oct 2002 16:07:02 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=221 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=219 <div><strong>Rev 219 - mohor</strong> (1 file(s) modified)</div><div>txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Fri, 11 Oct 2002 15:35:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=219 BIST added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=210 <div><strong>Rev 210 - mohor</strong> (3 file(s) modified)</div><div>BIST added.</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 10 Oct 2002 16:29:30 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=210 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=167 <div><strong>Rev 167 - mohor</strong> (1 file(s) modified)</div><div>Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 11 Sep 2002 14:18:46 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=167 Reception is possible after RxPointer is read and not after ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=166 <div><strong>Rev 166 - mohor</strong> (1 file(s) modified)</div><div>Reception is possible after RxPointer is read and not after ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 10 Sep 2002 13:48:46 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=166 Ethernet debug registers removed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=164 <div><strong>Rev 164 - mohor</strong> (3 file(s) modified)</div><div>Ethernet debug registers removed.</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 10 Sep 2002 10:35:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=164 Async reset for WB_ACK_O removed (when core was in reset, ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=159 <div><strong>Rev 159 - mohor</strong> (1 file(s) modified)</div><div>Async reset for WB_ACK_O removed (when core was in reset, ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Sun, 08 Sep 2002 16:31:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=159 Debug registers reg1, 2, 3, 4 connected. Synchronization of many ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=150 <div><strong>Rev 150 - mohor</strong> (1 file(s) modified)</div><div>Debug registers reg1, 2, 3, 4 connected. Synchronization of many ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 04 Sep 2002 18:47:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=150 Register TX_BD_NUM is changed so it contains value of the ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=134 <div><strong>Rev 134 - mohor</strong> (2 file(s) modified)</div><div>Register TX_BD_NUM is changed so it contains value of the ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 14 Aug 2002 19:31:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=134 WriteRxDataToMemory signal changed so end of frame (when last word ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=127 <div><strong>Rev 127 - mohor</strong> (1 file(s) modified)</div><div>WriteRxDataToMemory signal changed so end of frame (when last word ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 25 Jul 2002 18:29:01 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=127 Ram , used for BDs changed from generic_spram to eth_spram_256x32. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=119 <div><strong>Rev 119 - mohor</strong> (2 file(s) modified)</div><div>Ram , used for BDs changed from generic_spram to eth_spram_256x32.</div>~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Tue, 23 Jul 2002 15:28:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=119 ShiftEnded synchronization changed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=118 <div><strong>Rev 118 - mohor</strong> (1 file(s) modified)</div><div>ShiftEnded synchronization changed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Sat, 20 Jul 2002 00:41:32 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=118 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=115 <div><strong>Rev 115 - mohor</strong> (1 file(s) modified)</div><div>RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 18 Jul 2002 16:11:46 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=115 RxPointer bug fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=113 <div><strong>Rev 113 - mohor</strong> (1 file(s) modified)</div><div>RxPointer bug fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Thu, 11 Jul 2002 02:53:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=113 Previous bug wasn't succesfully removed. Now fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=112 <div><strong>Rev 112 - mohor</strong> (1 file(s) modified)</div><div>Previous bug wasn't succesfully removed. Now fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> mohor Wed, 10 Jul 2002 13:12:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_7%2Frtl%2Fverilog%2F&rev=112
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