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ethmac
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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&
Fri, 29 Mar 2024 07:48:38 +0100
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https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />
root
Tue, 05 May 2009 15:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=338
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 10:03:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=335
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This commit was manufactured by cvs2svn to create tag 'rel_8'.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=230
<div><strong>Rev 230 - </strong> (5 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_8'.</div>+ /tags/rel_8<br />- /tags/rel_8/bench<br />- /tags/rel_8/doc<br />- /tags/rel_8/README.txt<br />- /tags/rel_8/sim<br />
Fri, 18 Oct 2002 20:53:35 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=230
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case changed to casex.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=229
<div><strong>Rev 229 - mohor</strong> (1 file(s) modified)</div><div>case changed to casex.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Fri, 18 Oct 2002 20:53:34 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=229
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Changed BIST scan signals.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=227
<div><strong>Rev 227 - tadejm</strong> (5 file(s) modified)</div><div>Changed BIST scan signals.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
tadejm
Fri, 18 Oct 2002 17:04:20 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=227
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Igor added WB burst support and repaired BUG when handling ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=226
<div><strong>Rev 226 - tadejm</strong> (1 file(s) modified)</div><div>Igor added WB burst support and repaired BUG when handling ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
tadejm
Fri, 18 Oct 2002 15:42:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=226
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TxStatus is written after last access to the TX fifo ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=221
<div><strong>Rev 221 - mohor</strong> (1 file(s) modified)</div><div>TxStatus is written after last access to the TX fifo ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Mon, 14 Oct 2002 16:07:02 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=221
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txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=219
<div><strong>Rev 219 - mohor</strong> (1 file(s) modified)</div><div>txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Fri, 11 Oct 2002 15:35:20 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=219
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Typo error fixed. (When using Bist)
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=218
<div><strong>Rev 218 - mohor</strong> (1 file(s) modified)</div><div>Typo error fixed. (When using Bist)</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Fri, 11 Oct 2002 13:36:58 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=218
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Signals for WISHBONE B3 compliant interface added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=214
<div><strong>Rev 214 - mohor</strong> (1 file(s) modified)</div><div>Signals for WISHBONE B3 compliant interface added.</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Thu, 10 Oct 2002 16:49:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=214
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Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=213
<div><strong>Rev 213 - mohor</strong> (1 file(s) modified)</div><div>Defines changed to have ETH_ prolog.<br />
ETH_WISHBONE_B# define added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />
mohor
Thu, 10 Oct 2002 16:47:44 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=213
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Minor $display change.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=212
<div><strong>Rev 212 - mohor</strong> (1 file(s) modified)</div><div>Minor $display change.</div>~ /trunk/rtl/verilog/eth_cop.v<br />
mohor
Thu, 10 Oct 2002 16:43:59 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=212
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Bist added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=211
<div><strong>Rev 211 - mohor</strong> (1 file(s) modified)</div><div>Bist added.</div>~ /trunk/rtl/verilog/eth_defines.v<br />
mohor
Thu, 10 Oct 2002 16:33:11 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=211
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BIST added.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=210
<div><strong>Rev 210 - mohor</strong> (3 file(s) modified)</div><div>BIST added.</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Thu, 10 Oct 2002 16:29:30 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=210
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ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=204
<div><strong>Rev 204 - mohor</strong> (1 file(s) modified)</div><div>ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br />
mohor
Mon, 23 Sep 2002 18:24:31 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=204
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Virtual Silicon RAM might be used in the ASIC implementation ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=203
<div><strong>Rev 203 - mohor</strong> (1 file(s) modified)</div><div>Virtual Silicon RAM might be used in the ASIC implementation ...</div>~ /trunk/rtl/verilog/eth_defines.v<br />
mohor
Mon, 23 Sep 2002 18:22:48 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=203
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CsMiss added. When address between 0x800 and 0xfff is accessed ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=202
<div><strong>Rev 202 - mohor</strong> (1 file(s) modified)</div><div>CsMiss added. When address between 0x800 and 0xfff is accessed ...</div>~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Fri, 20 Sep 2002 17:12:58 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=202
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CarrierSenseLost bug fixed when operating in full duplex mode.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=168
<div><strong>Rev 168 - mohor</strong> (3 file(s) modified)</div><div>CarrierSenseLost bug fixed when operating in full duplex mode.</div>+ /trunk/rtl/verilog/BUGS<br />~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_top.v<br />
mohor
Thu, 12 Sep 2002 14:50:17 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=168
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Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=167
<div><strong>Rev 167 - mohor</strong> (1 file(s) modified)</div><div>Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Wed, 11 Sep 2002 14:18:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=167
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Reception is possible after RxPointer is read and not after ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=166
<div><strong>Rev 166 - mohor</strong> (1 file(s) modified)</div><div>Reception is possible after RxPointer is read and not after ...</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
mohor
Tue, 10 Sep 2002 13:48:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftags%2Frel_8%2Frtl%2F&rev=166
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