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ethmac WebSVN RSS feed - ethmac https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftrunk%2F& Mon, 16 Sep 2019 04:09:01 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=338 <div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br /> root Tue, 05 May 2009 15:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2F&rev=338 New directory structure. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethernet%2Ftrunk%2F&rev=335 <div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 10:03:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethernet%2Ftrunk%2F&rev=335 Minor fixes for Icarus simulator. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=334 <div><strong>Rev 334 - igorm</strong> (1 file(s) modified)</div><div>Minor fixes for Icarus simulator.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> igorm Tue, 22 Mar 2005 07:56:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=334 Some small fixes + some troubles fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=333 <div><strong>Rev 333 - igorm</strong> (5 file(s) modified)</div><div>Some small fixes + some troubles fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 21 Mar 2005 20:07:18 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=333 Case statement improved for synthesys. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=332 <div><strong>Rev 332 - igorm</strong> (1 file(s) modified)</div><div>Case statement improved for synthesys.</div>~ /trunk/rtl/verilog/eth_shiftreg.v<br /> igorm Tue, 08 Mar 2005 14:45:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=332 Tests for delayed CRC and defer indication added. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=331 <div><strong>Rev 331 - igorm</strong> (1 file(s) modified)</div><div>Tests for delayed CRC and defer indication added.</div>~ /trunk/bench/verilog/tb_ethernet.v<br /> igorm Mon, 21 Feb 2005 13:02:13 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=331 Warning fixes. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=330 <div><strong>Rev 330 - igorm</strong> (6 file(s) modified)</div><div>Warning fixes.</div>~ /trunk/rtl/verilog/eth_clockgen.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_fifo.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> igorm Mon, 21 Feb 2005 12:48:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=330 Defer indication fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=329 <div><strong>Rev 329 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 21 Feb 2005 11:35:33 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=329 Delayed CRC fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=328 <div><strong>Rev 328 - igorm</strong> (2 file(s) modified)</div><div>Delayed CRC fixed.</div>~ /trunk/rtl/verilog/eth_txcounters.v<br />~ /trunk/rtl/verilog/eth_txethmac.v<br /> igorm Mon, 21 Feb 2005 11:25:28 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=328 Defer indication fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=327 <div><strong>Rev 327 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_top.v<br /> igorm Mon, 21 Feb 2005 11:13:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=327 Delayed CRC fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=326 <div><strong>Rev 326 - igorm</strong> (1 file(s) modified)</div><div>Delayed CRC fixed.</div>~ /trunk/rtl/verilog/eth_rxcounters.v<br /> igorm Mon, 21 Feb 2005 11:00:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=326 Defer indication fixed. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=325 <div><strong>Rev 325 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br /> igorm Mon, 21 Feb 2005 10:42:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=325 Accidently deleted line put back. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=323 <div><strong>Rev 323 - igorm</strong> (1 file(s) modified)</div><div>Accidently deleted line put back.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Fri, 30 Apr 2004 10:30:00 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=323 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=321 <div><strong>Rev 321 - igorm</strong> (4 file(s) modified)</div><div>- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br /> igorm Mon, 26 Apr 2004 15:26:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=321 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=320 <div><strong>Rev 320 - igorm</strong> (1 file(s) modified)</div><div>TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.</div>~ /trunk/rtl/verilog/eth_registers.v<br /> igorm Mon, 26 Apr 2004 11:42:17 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=320 Latest Ethernet IP core testbench. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=319 <div><strong>Rev 319 - tadejm</strong> (4 file(s) modified)</div><div>Latest Ethernet IP core testbench.</div>+ /trunk/sim/rtl_sim/ncsim_sim/log/eth_tb.log<br />+ /trunk/sim/rtl_sim/ncsim_sim/log/tb_eth_display.log<br />~ /trunk/sim/rtl_sim/ncsim_sim/run/run_eth_sim_regr.scr<br />~ /trunk/sim/rtl_sim/ncsim_sim/run/top_groups.do<br /> tadejm Fri, 26 Mar 2004 16:07:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=319 Latest Ethernet IP core testbench. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=318 <div><strong>Rev 318 - tadejm</strong> (2 file(s) modified)</div><div>Latest Ethernet IP core testbench.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/wb_slave_behavioral.v<br /> tadejm Fri, 26 Mar 2004 15:59:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=318 Multicast detection fixed. Only the LSB of the first byte ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=317 <div><strong>Rev 317 - igorm</strong> (1 file(s) modified)</div><div>Multicast detection fixed. Only the LSB of the first byte ...</div>~ /trunk/rtl/verilog/eth_rxethmac.v<br /> igorm Wed, 17 Mar 2004 09:32:15 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=317 Updated testbench. Some more testcases, some repaired. https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=315 <div><strong>Rev 315 - tadejm</strong> (3 file(s) modified)</div><div>Updated testbench. Some more testcases, some repaired.</div>~ /trunk/bench/verilog/tb_ethernet.v<br />~ /trunk/bench/verilog/wb_bus_mon.v<br />~ /trunk/bench/verilog/wb_model_defines.v<br /> tadejm Fri, 05 Dec 2003 12:46:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=315 Corrected address mismatch for xilinx RAMB4_S8 model which has wider ... https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=312 <div><strong>Rev 312 - tadejm</strong> (1 file(s) modified)</div><div>Corrected address mismatch for xilinx RAMB4_S8 model which has wider ...</div>~ /trunk/rtl/verilog/eth_spram_256x32.v<br /> tadejm Fri, 05 Dec 2003 12:43:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Ftrunk%2F&rev=312
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