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ethmac
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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&
Thu, 28 Mar 2024 15:16:37 +0100
FeedCreator 1.7.2
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Whitespace cleanup
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=354
<div><strong>Rev 354 - olof</strong> (10 file(s) modified)</div><div>Whitespace cleanup</div>~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Thu, 04 Aug 2011 17:51:00 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=354
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Inherit fixes for bit width of constants from ORPSoC
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=353
<div><strong>Rev 353 - olof</strong> (6 file(s) modified)</div><div>Inherit fixes for bit width of constants from ORPSoC</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />
olof
Tue, 02 Aug 2011 16:18:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=353
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Removed delayed assignments from rtl code
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=352
<div><strong>Rev 352 - olof</strong> (24 file(s) modified)</div><div>Removed delayed assignments from rtl code</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Fri, 29 Jul 2011 10:25:44 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=352
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Turn defines into parameters in eth_cop
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=351
<div><strong>Rev 351 - olof</strong> (2 file(s) modified)</div><div>Turn defines into parameters in eth_cop</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:35:36 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=351
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Turn M[1-2]_ADDRESSED_S[1-2] defines into wires
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=350
<div><strong>Rev 350 - olof</strong> (2 file(s) modified)</div><div>Turn M[1-2]_ADDRESSED_S[1-2] defines into wires</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:00:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=350
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Make all parameters configurable from top level
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=349
<div><strong>Rev 349 - olof</strong> (6 file(s) modified)</div><div>Make all parameters configurable from top level</div>~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Tue, 19 Jul 2011 19:22:42 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=349
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Updated project location
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=346
<div><strong>Rev 346 - olof</strong> (36 file(s) modified)</div><div>Updated project location</div>~ /ethmac/trunk/bench/verilog/eth_host.v<br />~ /ethmac/trunk/bench/verilog/eth_memory.v<br />~ /ethmac/trunk/bench/verilog/eth_phy.v<br />~ /ethmac/trunk/bench/verilog/eth_phy_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_defines.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />~ /ethmac/trunk/bench/verilog/wb_master32.v<br />~ /ethmac/trunk/bench/verilog/wb_master_behavioral.v<br />~ /ethmac/trunk/bench/verilog/wb_model_defines.v<br />~ /ethmac/trunk/bench/verilog/wb_slave_behavioral.v<br />~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/rtl/verilog/timescale.v<br />
olof
Mon, 18 Jul 2011 17:38:57 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=346
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Reset AdressMiss signal on new frames to prevent reporting the ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=341
<div><strong>Rev 341 - olof</strong> (2 file(s) modified)</div><div>Reset AdressMiss signal on new frames to prevent reporting the ...</div>~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />
olof
Fri, 08 Jul 2011 17:44:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=341
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...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=338
<div><strong>Rev 338 - root</strong> (2 file(s) modified)</div><div>...</div>- /ethernet<br />+ /ethmac<br />
root
Tue, 05 May 2009 15:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=338
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=335
<div><strong>Rev 335 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /ethernet<br />+ /ethernet/branches<br />+ /ethernet/tags<br />+ /ethernet/trunk<br />+ /ethernet/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 10:03:10 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=335
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Some small fixes + some troubles fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=333
<div><strong>Rev 333 - igorm</strong> (5 file(s) modified)</div><div>Some small fixes + some troubles fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
igorm
Mon, 21 Mar 2005 20:07:18 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=333
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Case statement improved for synthesys.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=332
<div><strong>Rev 332 - igorm</strong> (1 file(s) modified)</div><div>Case statement improved for synthesys.</div>~ /trunk/rtl/verilog/eth_shiftreg.v<br />
igorm
Tue, 08 Mar 2005 14:45:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=332
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Warning fixes.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=330
<div><strong>Rev 330 - igorm</strong> (6 file(s) modified)</div><div>Warning fixes.</div>~ /trunk/rtl/verilog/eth_clockgen.v<br />~ /trunk/rtl/verilog/eth_defines.v<br />~ /trunk/rtl/verilog/eth_fifo.v<br />~ /trunk/rtl/verilog/eth_miim.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_spram_256x32.v<br />
igorm
Mon, 21 Feb 2005 12:48:07 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=330
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Defer indication fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=329
<div><strong>Rev 329 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
igorm
Mon, 21 Feb 2005 11:35:33 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=329
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Delayed CRC fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=328
<div><strong>Rev 328 - igorm</strong> (2 file(s) modified)</div><div>Delayed CRC fixed.</div>~ /trunk/rtl/verilog/eth_txcounters.v<br />~ /trunk/rtl/verilog/eth_txethmac.v<br />
igorm
Mon, 21 Feb 2005 11:25:28 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=328
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Defer indication fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=327
<div><strong>Rev 327 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_top.v<br />
igorm
Mon, 21 Feb 2005 11:13:17 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=327
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Delayed CRC fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=326
<div><strong>Rev 326 - igorm</strong> (1 file(s) modified)</div><div>Delayed CRC fixed.</div>~ /trunk/rtl/verilog/eth_rxcounters.v<br />
igorm
Mon, 21 Feb 2005 11:00:57 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=326
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Defer indication fixed.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=325
<div><strong>Rev 325 - igorm</strong> (1 file(s) modified)</div><div>Defer indication fixed.</div>~ /trunk/rtl/verilog/eth_macstatus.v<br />
igorm
Mon, 21 Feb 2005 10:42:11 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=325
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Accidently deleted line put back.
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=323
<div><strong>Rev 323 - igorm</strong> (1 file(s) modified)</div><div>Accidently deleted line put back.</div>~ /trunk/rtl/verilog/eth_wishbone.v<br />
igorm
Fri, 30 Apr 2004 10:30:00 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=323
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- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=321
<div><strong>Rev 321 - igorm</strong> (4 file(s) modified)</div><div>- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came ...</div>~ /trunk/rtl/verilog/eth_registers.v<br />~ /trunk/rtl/verilog/eth_rxethmac.v<br />~ /trunk/rtl/verilog/eth_top.v<br />~ /trunk/rtl/verilog/eth_wishbone.v<br />
igorm
Mon, 26 Apr 2004 15:26:23 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2Fethmac%2Ftrunk%2Frtl%2Fverilog%2F&rev=321
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