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ft816float WebSVN RSS feed - ft816float https://opencores.org/websvn//websvn/listing?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F& Tue, 17 Mar 2026 02:24:30 +0100 FeedCreator 1.7.2 - DPFTrunc() function https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=88 <div><strong>Rev 88 - robfinch</strong> (7 file(s) modified)</div><div>- DPFTrunc() function</div>+ /ft816float/trunk/rtl/verilog2/DFP32To96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFP64To96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPPkg.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPTrunc96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPUnpack.sv<br />+ /ft816float/trunk/software/FloatToString.asm<br />+ /ft816float/trunk/software/GetFloat.asm<br /> robfinch Fri, 30 Dec 2022 00:07:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=88 - improve divider *10 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=86 <div><strong>Rev 86 - robfinch</strong> (1 file(s) modified)</div><div>- improve divider *10</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.sv<br /> robfinch Wed, 14 Dec 2022 21:48:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=86 - improve divider *10 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=85 <div><strong>Rev 85 - robfinch</strong> (1 file(s) modified)</div><div>- improve divider *10</div>~ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br /> robfinch Wed, 14 Dec 2022 21:48:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=85 - improve DPD divider https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=84 <div><strong>Rev 84 - robfinch</strong> (1 file(s) modified)</div><div>- improve DPD divider</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.sv<br /> robfinch Wed, 14 Dec 2022 18:53:25 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=84 - sign of zero is positive https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=83 <div><strong>Rev 83 - robfinch</strong> (2 file(s) modified)</div><div>- sign of zero is positive</div>~ /ft816float/trunk/rtl/verilog2/BCDSubtract.sv<br />- /ft816float/trunk/rtl/verilog2/dfdiv.v<br /> robfinch Wed, 14 Dec 2022 16:37:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=83 - improved divider https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=82 <div><strong>Rev 82 - robfinch</strong> (2 file(s) modified)</div><div>- improved divider</div>+ /ft816float/trunk/rtl/verilog2/dfdiv.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br /> robfinch Wed, 14 Dec 2022 16:13:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=82 - timing delay on divide - change adder in multiply https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=81 <div><strong>Rev 81 - robfinch</strong> (4 file(s) modified)</div><div>- timing delay on divide<br /> - change adder in multiply</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />~ /ft816float/trunk/rtl/verilog2/dfmul.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br /> robfinch Wed, 14 Dec 2022 06:36:16 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=81 - improve decimal float divide https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=80 <div><strong>Rev 80 - robfinch</strong> (9 file(s) modified)</div><div>- improve decimal float divide</div>~ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDMath.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDSubtract.sv<br />+ /ft816float/trunk/rtl/verilog2/DDBinToBCDFract.sv<br />+ /ft816float/trunk/rtl/verilog2/dfdiv2.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPCompare96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br />+ /ft816float/trunk/test_bench/DFPDivide96_tb.v<br /> robfinch Wed, 14 Dec 2022 00:52:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=80 - fix sticky infinity https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=79 <div><strong>Rev 79 - robfinch</strong> (1 file(s) modified)</div><div>- fix sticky infinity</div>~ /ft816float/trunk/rtl/verilog2/DFPScaleb96.sv<br /> robfinch Mon, 12 Dec 2022 17:09:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=79 - BCD subtraction - scaleb function https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=78 <div><strong>Rev 78 - robfinch</strong> (10 file(s) modified)</div><div>- BCD subtraction<br /> - scaleb function</div>~ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />+ /ft816float/trunk/rtl/verilog2/BCDSubtract.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPNormalize96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPRound96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPScaleb96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPSqrt96.sv<br />~ /ft816float/trunk/test_bench/DFPAddsub96_tb.v<br />+ /ft816float/trunk/test_bench/DFPScaleb96_tb.v<br />~ /ft816float/trunk/test_bench/i2df128_tb.sv<br /> robfinch Mon, 12 Dec 2022 05:20:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=78 - adjust 9 to 7 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=76 <div><strong>Rev 76 - robfinch</strong> (1 file(s) modified)</div><div>- adjust 9 to 7</div>~ /ft816float/trunk/rtl/verilog2/i2df96.sv<br /> robfinch Sat, 10 Dec 2022 05:32:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=76 - add triple precision decimal float https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=75 <div><strong>Rev 75 - robfinch</strong> (12 file(s) modified)</div><div>- add triple precision decimal float</div>+ /ft816float/trunk/rtl/verilog2/df96Toi.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPCompare96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPMultiply96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPNormalize96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPPack.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPPkg.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPRound96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPSqrt96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPUnpack.sv<br />+ /ft816float/trunk/rtl/verilog2/i2df96.sv<br /> robfinch Sat, 10 Dec 2022 00:07:31 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=75 - added single precision combo logic only version of FMA https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=74 <div><strong>Rev 74 - robfinch</strong> (8 file(s) modified)</div><div>- added single precision combo logic only version of FMA</div>+ /ft816float/trunk/rtl/verilog2/fpFMA32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/fpNormalize32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/fpRound32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/mult16x16combo.sv<br />+ /ft816float/trunk/rtl/verilog2/mult32x32combo.sv<br />+ /ft816float/trunk/test_bench/fpFMA32combo_tb.sv<br />+ /ft816float/trunk/test_bench/fpFMA32_tv.txt<br />+ /ft816float/trunk/test_bench/fpFMA32_tvo.txt<br /> robfinch Wed, 24 Aug 2022 06:32:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=74 - fix Karatsuba carry chain bug https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=73 <div><strong>Rev 73 - robfinch</strong> (10 file(s) modified)</div><div>- fix Karatsuba carry chain bug</div>~ /ft816float/trunk/rtl/verilog2/mult32x32.sv<br />~ /ft816float/trunk/rtl/verilog2/mult64x64.sv<br />~ /ft816float/trunk/rtl/verilog2/mult128x128.sv<br />+ /ft816float/trunk/rtl/verilog2/mult128x128seq.sv<br />~ /ft816float/trunk/test_bench/mult32x32_tb.sv<br />~ /ft816float/trunk/test_bench/mult32x32_tvo.txt<br />+ /ft816float/trunk/test_bench/mult64x64_tb.sv<br />+ /ft816float/trunk/test_bench/mult64x64_tvo.txt<br />+ /ft816float/trunk/test_bench/mult128x128_tb.sv<br />+ /ft816float/trunk/test_bench/mult128x128_tvo.txt<br /> robfinch Sun, 06 Mar 2022 06:21:41 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=73 - fix: mult32x32 prod high order bits https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=72 <div><strong>Rev 72 - robfinch</strong> (5 file(s) modified)</div><div>- fix: mult32x32 prod high order bits</div>~ /ft816float/trunk/rtl/verilog2/mult32x32.sv<br />~ /ft816float/trunk/rtl/verilog2/mult64x64.sv<br />~ /ft816float/trunk/rtl/verilog2/mult128x128.sv<br />+ /ft816float/trunk/test_bench/mult32x32_tb.sv<br />+ /ft816float/trunk/test_bench/mult32x32_tvo.txt<br /> robfinch Sun, 06 Mar 2022 03:48:05 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=72 - added decimal float reciprocal estimate https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=71 <div><strong>Rev 71 - robfinch</strong> (1 file(s) modified)</div><div>- added decimal float reciprocal estimate</div>+ /ft816float/trunk/rtl/verilog2/DFPRes128.sv<br /> robfinch Sat, 26 Feb 2022 07:26:33 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=71 - fix carry out for BCD add / sub https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=70 <div><strong>Rev 70 - robfinch</strong> (7 file(s) modified)</div><div>- fix carry out for BCD add / sub</div>~ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDMath.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDSub8NClk.sv<br />~ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub128.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPMultiply128.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPRound128.sv<br /> robfinch Sat, 26 Feb 2022 00:36:45 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=70 - added decimal float compare https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=68 <div><strong>Rev 68 - robfinch</strong> (1 file(s) modified)</div><div>- added decimal float compare</div>+ /ft816float/trunk/rtl/verilog2/DFPCompare128.sv<br /> robfinch Tue, 22 Feb 2022 01:54:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=68 - adding decimal float divide https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=67 <div><strong>Rev 67 - robfinch</strong> (3 file(s) modified)</div><div>- adding decimal float divide</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />+ /ft816float/trunk/rtl/verilog2/DFPDivide128.sv<br />+ /ft816float/trunk/test_bench/DFPDivide128_tb.v<br /> robfinch Mon, 21 Feb 2022 22:14:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=67 - BCD arith additions https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=66 <div><strong>Rev 66 - robfinch</strong> (3 file(s) modified)</div><div>- BCD arith additions</div>+ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />+ /ft816float/trunk/rtl/verilog2/BCDMath.sv<br />+ /ft816float/trunk/rtl/verilog2/BCDSub8NClk.sv<br /> robfinch Mon, 21 Feb 2022 20:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Frtl%2Fverilog2%2F&rev=66

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