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ft816float WebSVN RSS feed - ft816float https://opencores.org/websvn//websvn/listing?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F& Fri, 08 May 2026 15:09:52 +0100 FeedCreator 1.7.2 - sin / cosine https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=90 <div><strong>Rev 90 - robfinch</strong> (11 file(s) modified)</div><div>- sin / cosine</div>+ /ft816float/trunk/rtl/verilog2/fpCompare32.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCompare64.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCompare128.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCordic.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCvt16To64.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCvt16To128.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCvt32To64.sv<br />+ /ft816float/trunk/rtl/verilog2/fpCvt64To128.sv<br />+ /ft816float/trunk/rtl/verilog2/fpDecomp128Reg.sv<br />+ /ft816float/trunk/rtl/verilog2/fpSincos64.sv<br />+ /ft816float/trunk/test_bench/fpSincos_tb.sv<br /> robfinch Sat, 03 Jun 2023 15:25:51 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=90 - improve decimal float divide https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=80 <div><strong>Rev 80 - robfinch</strong> (9 file(s) modified)</div><div>- improve decimal float divide</div>~ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDMath.sv<br />~ /ft816float/trunk/rtl/verilog2/BCDSubtract.sv<br />+ /ft816float/trunk/rtl/verilog2/DDBinToBCDFract.sv<br />+ /ft816float/trunk/rtl/verilog2/dfdiv2.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPCompare96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDivide96.sv<br />+ /ft816float/trunk/test_bench/DFPDivide96_tb.v<br /> robfinch Wed, 14 Dec 2022 00:52:57 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=80 - BCD subtraction - scaleb function https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=78 <div><strong>Rev 78 - robfinch</strong> (10 file(s) modified)</div><div>- BCD subtraction<br /> - scaleb function</div>~ /ft816float/trunk/rtl/verilog2/BCDAdd8NClk.sv<br />+ /ft816float/trunk/rtl/verilog2/BCDSubtract.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPNormalize96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPRound96.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPScaleb96.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPSqrt96.sv<br />~ /ft816float/trunk/test_bench/DFPAddsub96_tb.v<br />+ /ft816float/trunk/test_bench/DFPScaleb96_tb.v<br />~ /ft816float/trunk/test_bench/i2df128_tb.sv<br /> robfinch Mon, 12 Dec 2022 05:20:24 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=78 - test benches https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=77 <div><strong>Rev 77 - robfinch</strong> (3 file(s) modified)</div><div>- test benches</div>+ /ft816float/trunk/test_bench/DFPAddsub96_tb.v<br />+ /ft816float/trunk/test_bench/DFPMultiply96_tb.v<br />+ /ft816float/trunk/test_bench/i2df96_tb.sv<br /> robfinch Sat, 10 Dec 2022 05:34:27 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=77 - added single precision combo logic only version of FMA https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=74 <div><strong>Rev 74 - robfinch</strong> (8 file(s) modified)</div><div>- added single precision combo logic only version of FMA</div>+ /ft816float/trunk/rtl/verilog2/fpFMA32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/fpNormalize32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/fpRound32combo.sv<br />+ /ft816float/trunk/rtl/verilog2/mult16x16combo.sv<br />+ /ft816float/trunk/rtl/verilog2/mult32x32combo.sv<br />+ /ft816float/trunk/test_bench/fpFMA32combo_tb.sv<br />+ /ft816float/trunk/test_bench/fpFMA32_tv.txt<br />+ /ft816float/trunk/test_bench/fpFMA32_tvo.txt<br /> robfinch Wed, 24 Aug 2022 06:32:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=74 - fix Karatsuba carry chain bug https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=73 <div><strong>Rev 73 - robfinch</strong> (10 file(s) modified)</div><div>- fix Karatsuba carry chain bug</div>~ /ft816float/trunk/rtl/verilog2/mult32x32.sv<br />~ /ft816float/trunk/rtl/verilog2/mult64x64.sv<br />~ /ft816float/trunk/rtl/verilog2/mult128x128.sv<br />+ /ft816float/trunk/rtl/verilog2/mult128x128seq.sv<br />~ /ft816float/trunk/test_bench/mult32x32_tb.sv<br />~ /ft816float/trunk/test_bench/mult32x32_tvo.txt<br />+ /ft816float/trunk/test_bench/mult64x64_tb.sv<br />+ /ft816float/trunk/test_bench/mult64x64_tvo.txt<br />+ /ft816float/trunk/test_bench/mult128x128_tb.sv<br />+ /ft816float/trunk/test_bench/mult128x128_tvo.txt<br /> robfinch Sun, 06 Mar 2022 06:21:41 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=73 - fix: mult32x32 prod high order bits https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=72 <div><strong>Rev 72 - robfinch</strong> (5 file(s) modified)</div><div>- fix: mult32x32 prod high order bits</div>~ /ft816float/trunk/rtl/verilog2/mult32x32.sv<br />~ /ft816float/trunk/rtl/verilog2/mult64x64.sv<br />~ /ft816float/trunk/rtl/verilog2/mult128x128.sv<br />+ /ft816float/trunk/test_bench/mult32x32_tb.sv<br />+ /ft816float/trunk/test_bench/mult32x32_tvo.txt<br /> robfinch Sun, 06 Mar 2022 03:48:05 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=72 - test bench for compare https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=69 <div><strong>Rev 69 - robfinch</strong> (1 file(s) modified)</div><div>- test bench for compare</div>+ /ft816float/trunk/test_bench/DFPCompare128_tb.v<br /> robfinch Tue, 22 Feb 2022 01:55:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=69 - adding decimal float divide https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=67 <div><strong>Rev 67 - robfinch</strong> (3 file(s) modified)</div><div>- adding decimal float divide</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />+ /ft816float/trunk/rtl/verilog2/DFPDivide128.sv<br />+ /ft816float/trunk/test_bench/DFPDivide128_tb.v<br /> robfinch Mon, 21 Feb 2022 22:14:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=67 - add multiply 128 - fix exponent bias https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=64 <div><strong>Rev 64 - robfinch</strong> (8 file(s) modified)</div><div>- add multiply 128<br /> - fix exponent bias</div>~ /ft816float/trunk/rtl/verilog2/df128Toi.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub128.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPMultiply128.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPRound128.sv<br />~ /ft816float/trunk/rtl/verilog2/i2df128.sv<br />~ /ft816float/trunk/test_bench/df128Toi_tb.sv<br />+ /ft816float/trunk/test_bench/DFPAddsub128_tb.v<br />+ /ft816float/trunk/test_bench/DFPMultiply128_tb.v<br /> robfinch Mon, 21 Feb 2022 19:59:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=64 - fix overflow status - license comment https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=62 <div><strong>Rev 62 - robfinch</strong> (3 file(s) modified)</div><div>- fix overflow status<br /> - license comment</div>~ /ft816float/trunk/rtl/verilog2/df128Toi.sv<br />~ /ft816float/trunk/test_bench/df128Toi_tb.sv<br />~ /ft816float/trunk/test_bench/i2df128_tb.sv<br /> robfinch Mon, 21 Feb 2022 06:48:37 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=62 - decimal float &lt;-&gt; int converters https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=60 <div><strong>Rev 60 - robfinch</strong> (4 file(s) modified)</div><div>- decimal float &lt;-&gt; int converters</div>+ /ft816float/trunk/rtl/verilog2/df128Toi.sv<br />+ /ft816float/trunk/rtl/verilog2/i2df128.sv<br />+ /ft816float/trunk/test_bench/df128Toi_tb.sv<br />+ /ft816float/trunk/test_bench/i2df128_tb.sv<br /> robfinch Mon, 21 Feb 2022 05:09:22 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=60 - bin to bcd and bcd to bin converters https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=59 <div><strong>Rev 59 - robfinch</strong> (4 file(s) modified)</div><div>- bin to bcd and bcd to bin converters</div>+ /ft816float/trunk/rtl/verilog2/DDBCDToBin.sv<br />+ /ft816float/trunk/rtl/verilog2/DDBinToBCD.sv<br />+ /ft816float/trunk/test_bench/DDBCDToBin_tb.sv<br />+ /ft816float/trunk/test_bench/DDBinToBCD_tb.sv<br /> robfinch Mon, 21 Feb 2022 00:52:19 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=59 - generic redor https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=58 <div><strong>Rev 58 - robfinch</strong> (5 file(s) modified)</div><div>- generic redor</div>~ /ft816float/trunk/rtl/verilog2/DFPAddsub128.sv<br />~ /ft816float/trunk/rtl/verilog2/fpFMA.sv<br />+ /ft816float/trunk/rtl/verilog2/redorN.sv<br />+ /ft816float/trunk/test_bench/fpFMA_tb.sv<br />~ /ft816float/trunk/test_bench/fpFMA_tvdo.txt<br /> robfinch Fri, 04 Jun 2021 20:05:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=58 - decimal square root function https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=56 <div><strong>Rev 56 - robfinch</strong> (6 file(s) modified)</div><div>- decimal square root function</div>~ /ft816float/trunk/rtl/verilog2/BCDMath.v<br />+ /ft816float/trunk/rtl/verilog2/dfisqrt.v<br />+ /ft816float/trunk/rtl/verilog2/DFPSqrt.sv<br />~ /ft816float/trunk/rtl/verilog2/DPD1000Decode.sv<br />~ /ft816float/trunk/rtl/verilog2/DPD1000Encode.sv<br />~ /ft816float/trunk/test_bench/DFPDivide_tb.v<br /> robfinch Sun, 20 Dec 2020 06:53:30 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=56 - add storage format - parameterization https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=55 <div><strong>Rev 55 - robfinch</strong> (13 file(s) modified)</div><div>- add storage format<br /> - parameterization</div>~ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />~ /ft816float/trunk/rtl/verilog2/dfmul.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPAddsub.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDecompose.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPDivide.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPMultiply.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPNormalize.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPRound.sv<br />+ /ft816float/trunk/rtl/verilog2/DPD1000Decode.sv<br />+ /ft816float/trunk/rtl/verilog2/DPD1000Encode.sv<br />~ /ft816float/trunk/test_bench/DFPAddsub_tb.v<br />~ /ft816float/trunk/test_bench/DFPDivide_tb.v<br />~ /ft816float/trunk/test_bench/DFPMultiply_tb.v<br /> robfinch Sat, 19 Dec 2020 14:30:46 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=55 - add decimal float divider https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=54 <div><strong>Rev 54 - robfinch</strong> (7 file(s) modified)</div><div>- add decimal float divider</div>~ /ft816float/trunk/rtl/verilog2/BCDMath.v<br />+ /ft816float/trunk/rtl/verilog2/dfdiv.v<br />+ /ft816float/trunk/rtl/verilog2/dfmul.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPDivide.sv<br />~ /ft816float/trunk/rtl/verilog2/DFPMultiply.sv<br />+ /ft816float/trunk/test_bench/DFPDivide_tb.v<br />+ /ft816float/trunk/test_bench/DFPMultiply_tb.v<br /> robfinch Sat, 19 Dec 2020 01:03:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=54 - test bench update https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=52 <div><strong>Rev 52 - robfinch</strong> (1 file(s) modified)</div><div>- test bench update</div>~ /ft816float/trunk/test_bench/DFPAddsub_tb.v<br /> robfinch Thu, 17 Dec 2020 18:10:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=52 - added decimal floating-point adder https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=50 <div><strong>Rev 50 - robfinch</strong> (6 file(s) modified)</div><div>- added decimal floating-point adder</div>+ /ft816float/trunk/rtl/verilog2/BCDMath.v<br />+ /ft816float/trunk/rtl/verilog2/DFPAddsub.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPDecompose.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPNormalize.sv<br />+ /ft816float/trunk/rtl/verilog2/DFPRound.sv<br />+ /ft816float/trunk/test_bench/DFPAddsub_tb.v<br /> robfinch Thu, 17 Dec 2020 09:46:40 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=50 - pipelining https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=49 <div><strong>Rev 49 - robfinch</strong> (16 file(s) modified)</div><div>- pipelining</div>~ /ft816float/trunk/rtl/verilog2/fp.sv<br />~ /ft816float/trunk/rtl/verilog2/fpAddsub.sv<br />~ /ft816float/trunk/rtl/verilog2/fpDivide.sv<br />~ /ft816float/trunk/rtl/verilog2/fpMultiply.sv<br />~ /ft816float/trunk/rtl/verilog2/fpNormalize.sv<br />~ /ft816float/trunk/rtl/verilog2/fpRound.sv<br />+ /ft816float/trunk/rtl/verilog2/mult16x16.sv<br />+ /ft816float/trunk/rtl/verilog2/mult32x32.sv<br />+ /ft816float/trunk/rtl/verilog2/mult64x64.sv<br />+ /ft816float/trunk/rtl/verilog2/mult128x128.sv<br />~ /ft816float/trunk/test_bench/fpAddsub_tb.v<br />~ /ft816float/trunk/test_bench/fpAddsub_tvo.txt<br />+ /ft816float/trunk/test_bench/fpDivide_tb.v<br />+ /ft816float/trunk/test_bench/fpDivide_tvo.txt<br />+ /ft816float/trunk/test_bench/fpMultiply_tb.v<br />+ /ft816float/trunk/test_bench/fpMultiply_tvo.txt<br /> robfinch Fri, 27 Nov 2020 05:08:23 +0100 https://opencores.org/websvn//websvn/revision?repname=ft816float&path=%2Fft816float%2Ftrunk%2Ftest_bench%2F&rev=49
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