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hicovec
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https://opencores.org/websvn//websvn/listing?repname=hicovec&path=%2Fhicovec%2Fbranches%2F&
Thu, 28 Mar 2024 16:42:14 +0100
FeedCreator 1.7.2
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fhicovec%2Fbranches%2F&rev=12
<div><strong>Rev 12 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /hicovec<br />+ /hicovec/branches<br />+ /hicovec/tags<br />+ /hicovec/trunk<br />+ /hicovec/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 22:19:17 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fhicovec%2Fbranches%2F&rev=12
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no message
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=8
<div><strong>Rev 8 - hmanske</strong> (5 file(s) modified)</div><div>no message</div>~ /branches/avendor/debugger/clvpdbg.py<br />+ /branches/avendor/debugger/readme.txt<br />+ /branches/avendor/documentation<br />+ /branches/avendor/documentation/diplomathesis.pdf<br />+ /branches/avendor/documentation/instructioncoding.txt<br />
hmanske
Thu, 25 Sep 2008 21:15:25 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=8
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no message
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=6
<div><strong>Rev 6 - hmanske</strong> (2 file(s) modified)</div><div>no message</div>+ /branches/avendor/diplomathesis.pdf<br />+ /branches/avendor/instructioncoding.txt<br />
hmanske
Thu, 25 Sep 2008 21:03:25 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=6
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no message
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=4
<div><strong>Rev 4 - hmanske</strong> (45 file(s) modified)</div><div>no message</div>~ /branches/avendor/assembler/clvpasm.py<br />~ /branches/avendor/assembler/cputest.txt<br />~ /branches/avendor/cpu/config.vhd<br />~ /branches/avendor/cpu/datatypes.vhd<br />~ /branches/avendor/cpu/groups/addressgroup.vhd<br />~ /branches/avendor/cpu/groups/aluinputgroup.vhd<br />~ /branches/avendor/cpu/groups/cpu.vhd<br />~ /branches/avendor/cpu/groups/flaggroup.vhd<br />~ /branches/avendor/cpu/groups/registergroup.vhd<br />~ /branches/avendor/cpu/groups/vector_executionunit.vhd<br />~ /branches/avendor/cpu/groups/vector_slice.vhd<br />~ /branches/avendor/cpu/system.vhd<br />~ /branches/avendor/cpu/testbenches/tb_addressgroup.vhd<br />~ /branches/avendor/cpu/testbenches/tb_alu.vhd<br />~ /branches/avendor/cpu/testbenches/tb_aluinputgroup.vhd<br />~ /branches/avendor/cpu/testbenches/tb_dataregister.vhd<br />~ /branches/avendor/cpu/testbenches/tb_demultiplexer1x4.vhd<br />~ /branches/avendor/cpu/testbenches/tb_flag.vhd<br />~ /branches/avendor/cpu/testbenches/tb_flaggroup.vhd<br />~ /branches/avendor/cpu/testbenches/tb_instructioncounter.vhd<br />~ /branches/avendor/cpu/testbenches/tb_multiplexer2.vhd<br />~ /branches/avendor/cpu/testbenches/tb_multiplexer4.vhd<br />~ /branches/avendor/cpu/testbenches/tb_registergroup.vhd<br />~ /branches/avendor/cpu/testbenches/tb_selectunit.vhd<br />~ /branches/avendor/cpu/testbenches/tb_system.vhd<br />~ /branches/avendor/cpu/testbenches/tb_vector_alu_32.vhd<br />~ /branches/avendor/cpu/testbenches/tb_vector_register.vhd<br />~ /branches/avendor/cpu/units/alu.vhd<br />~ /branches/avendor/cpu/units/controlunit.vhd<br />~ /branches/avendor/cpu/units/dataregister.vhd<br />~ /branches/avendor/cpu/units/debugger.vhd<br />~ /branches/avendor/cpu/units/demultiplexer1x4.vhd<br />~ /branches/avendor/cpu/units/flag.vhd<br />~ /branches/avendor/cpu/units/instructioncounter.vhd<br />~ /branches/avendor/cpu/units/memoryinterface.vhd<br />~ /branches/avendor/cpu/units/multiplexer2.vhd<br />~ /branches/avendor/cpu/units/multiplexer4.vhd<br />~ /branches/avendor/cpu/units/selectunit.vhd<br />~ /branches/avendor/cpu/units/shuffle.vhd<br />~ /branches/avendor/cpu/units/sram.vhd<br />~ /branches/avendor/cpu/units/valu_controlunit.vhd<br />~ /branches/avendor/cpu/units/vector_alu_32.vhd<br />~ /branches/avendor/cpu/units/vector_controlunit.vhd<br />~ /branches/avendor/cpu/units/vector_register.vhd<br />~ /branches/avendor/debugger/clvpdbg.py<br />
hmanske
Fri, 06 Jun 2008 10:27:10 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=4
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no message
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=2
<div><strong>Rev 2 - hmanske</strong> (56 file(s) modified)</div><div>no message</div>+ /branches/avendor<br />+ /branches/avendor/assembler<br />+ /branches/avendor/assembler/clvpasm.py<br />+ /branches/avendor/assembler/cputest.txt<br />+ /branches/avendor/assembler/pyparsing.py<br />+ /branches/avendor/cpu<br />+ /branches/avendor/cpu/config.vhd<br />+ /branches/avendor/cpu/constraints.ucf<br />+ /branches/avendor/cpu/datatypes.vhd<br />+ /branches/avendor/cpu/groups<br />+ /branches/avendor/cpu/groups/addressgroup.vhd<br />+ /branches/avendor/cpu/groups/aluinputgroup.vhd<br />+ /branches/avendor/cpu/groups/cpu.vhd<br />+ /branches/avendor/cpu/groups/flaggroup.vhd<br />+ /branches/avendor/cpu/groups/registergroup.vhd<br />+ /branches/avendor/cpu/groups/vector_executionunit.vhd<br />+ /branches/avendor/cpu/groups/vector_slice.vhd<br />+ /branches/avendor/cpu/system.vhd<br />+ /branches/avendor/cpu/testbenches<br />+ /branches/avendor/cpu/testbenches/tb_addressgroup.vhd<br />+ /branches/avendor/cpu/testbenches/tb_alu.vhd<br />+ /branches/avendor/cpu/testbenches/tb_aluinputgroup.vhd<br />+ /branches/avendor/cpu/testbenches/tb_dataregister.vhd<br />+ /branches/avendor/cpu/testbenches/tb_demultiplexer1x4.vhd<br />+ /branches/avendor/cpu/testbenches/tb_flag.vhd<br />+ /branches/avendor/cpu/testbenches/tb_flaggroup.vhd<br />+ /branches/avendor/cpu/testbenches/tb_instructioncounter.vhd<br />+ /branches/avendor/cpu/testbenches/tb_multiplexer2.vhd<br />+ /branches/avendor/cpu/testbenches/tb_multiplexer4.vhd<br />+ /branches/avendor/cpu/testbenches/tb_registergroup.vhd<br />+ /branches/avendor/cpu/testbenches/tb_selectunit.vhd<br />+ /branches/avendor/cpu/testbenches/tb_system.vhd<br />+ /branches/avendor/cpu/testbenches/tb_vector_alu_32.vhd<br />+ /branches/avendor/cpu/testbenches/tb_vector_register.vhd<br />+ /branches/avendor/cpu/units<br />+ /branches/avendor/cpu/units/alu.vhd<br />+ /branches/avendor/cpu/units/controlunit.vhd<br />+ /branches/avendor/cpu/units/dataregister.vhd<br />+ /branches/avendor/cpu/units/debugger.vhd<br />+ /branches/avendor/cpu/units/demultiplexer1x4.vhd<br />+ /branches/avendor/cpu/units/flag.vhd<br />+ /branches/avendor/cpu/units/instructioncounter.vhd<br />+ /branches/avendor/cpu/units/memoryinterface.vhd<br />+ /branches/avendor/cpu/units/multiplexer2.vhd<br />+ /branches/avendor/cpu/units/multiplexer4.vhd<br />+ /branches/avendor/cpu/units/rs232.vhd<br />+ /branches/avendor/cpu/units/selectunit.vhd<br />+ /branches/avendor/cpu/units/shuffle.vhd<br />+ /branches/avendor/cpu/units/sram.vhd<br />+ /branches/avendor/cpu/units/valu_controlunit.vhd<br />+ /branches/avendor/cpu/units/vector_alu_32.vhd<br />+ /branches/avendor/cpu/units/vector_controlunit.vhd<br />+ /branches/avendor/cpu/units/vector_register.vhd<br />+ /branches/avendor/debugger<br />+ /branches/avendor/debugger/clvpdbg.py<br />+ /branches/avendor/debugger/pyparsing.py<br />
hmanske
Fri, 06 Jun 2008 09:19:39 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=2
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Standard project directories initialized by cvs2svn.
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=1
<div><strong>Rev 1 - </strong> (3 file(s) modified)</div><div>Standard project directories initialized by cvs2svn.</div>+ /branches<br />+ /tags<br />+ /trunk<br />
Fri, 06 Jun 2008 09:19:39 +0100
https://opencores.org/websvn//websvn/revision?repname=hicovec&path=%2Fbranches%2F&rev=1
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