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i2c WebSVN RSS feed - i2c https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2F& Fri, 25 Sep 2020 01:38:54 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2F&rev=68 <div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 22:30:52 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2F&rev=68 Fixed slave_wait clocked event syntax https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=67 <div><strong>Rev 67 - rherveille</strong> (1 file(s) modified)</div><div>Fixed slave_wait clocked event syntax</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 04 Feb 2009 20:17:34 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=67 Fixed type iscl_oen instead of scl_oen https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=66 <div><strong>Rev 66 - rherveille</strong> (1 file(s) modified)</div><div>Fixed type iscl_oen instead of scl_oen</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 20 Jan 2009 20:40:36 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=66 Changed wb_adr_i from unsigned to std_logic_vector https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=65 <div><strong>Rev 65 - rherveille</strong> (1 file(s) modified)</div><div>Changed wb_adr_i from unsigned to std_logic_vector</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Tue, 20 Jan 2009 10:38:45 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=65 Added SCL clock synchronization logic Fixed slave_wait signal generation https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=64 <div><strong>Rev 64 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL clock synchronization logic<br /> Fixed slave_wait signal generation</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 20 Jan 2009 10:34:51 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=64 Added clock synchronization logic Fixed slave_wait signal https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=63 <div><strong>Rev 63 - rherveille</strong> (1 file(s) modified)</div><div>Added clock synchronization logic<br /> Fixed slave_wait signal</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Tue, 20 Jan 2009 10:25:29 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=63 Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=62 <div><strong>Rev 62 - rherveille</strong> (3 file(s) modified)</div><div>Fixed synopsys miss spell (synopsis)<br /> Fixed cr[0] register width<br /> Fixed ! usage ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Mon, 19 Jan 2009 20:29:26 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=62 Removed synopsys link; it's not used https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=61 <div><strong>Rev 61 - rherveille</strong> (1 file(s) modified)</div><div>Removed synopsys link; it's not used</div>~ /trunk/sim/i2c_verilog/run/run<br /> rherveille Fri, 06 Apr 2007 09:02:38 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=61 Added missing semicolons ';' on endif https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=60 <div><strong>Rev 60 - rherveille</strong> (1 file(s) modified)</div><div>Added missing semicolons ';' on endif</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 11 Oct 2006 12:10:13 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=60 fixed short scl high pulse after clock stretch https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=59 <div><strong>Rev 59 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 06 Oct 2006 10:48:24 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=59 fixed (n)ack generation https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=58 <div><strong>Rev 58 - rherveille</strong> (2 file(s) modified)</div><div>fixed (n)ack generation</div>~ /trunk/bench/verilog/i2c_slave_model.v<br />~ /trunk/bench/verilog/tst_bench_top.v<br /> rherveille Mon, 04 Sep 2006 09:08:51 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=58 fixed short scl high pulse after clock stretch fixed slave model ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=57 <div><strong>Rev 57 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch<br /> fixed slave model ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Mon, 04 Sep 2006 09:08:13 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=57 Fixed Tsu:sta timing check. Added Thd:sta timing check. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=56 <div><strong>Rev 56 - rherveille</strong> (1 file(s) modified)</div><div>Fixed Tsu:sta timing check.<br /> Added Thd:sta timing check.</div>~ /trunk/bench/verilog/i2c_slave_model.v<br /> rherveille Mon, 28 Feb 2005 11:33:48 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=56 Fixed register overwrite issue. Removed full_case pragma, replaced it by a ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=55 <div><strong>Rev 55 - rherveille</strong> (1 file(s) modified)</div><div>Fixed register overwrite issue.<br /> Removed full_case pragma, replaced it by a ...</div>~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Sun, 27 Feb 2005 09:26:24 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=55 Fixed scl, sda delay. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=54 <div><strong>Rev 54 - rherveille</strong> (1 file(s) modified)</div><div>Fixed scl, sda delay.</div>~ /trunk/bench/verilog/tst_bench_top.v<br /> rherveille Sun, 27 Feb 2005 09:24:18 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=54 Fixed previous fix :) Made a variable vs signal mistake. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=53 <div><strong>Rev 53 - rherveille</strong> (1 file(s) modified)</div><div>Fixed previous fix :) Made a variable vs signal mistake.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 07 May 2004 11:53:31 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=53 Fixed a bug where the core would signal an arbitration ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=52 <div><strong>Rev 52 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would signal an arbitration ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 07 May 2004 11:04:00 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=52 Fixed simulation issue when writing to CR register https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=51 <div><strong>Rev 51 - rherveille</strong> (1 file(s) modified)</div><div>Fixed simulation issue when writing to CR register</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sun, 14 Mar 2004 10:17:03 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=51 *** empty log message *** https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=50 <div><strong>Rev 50 - rherveille</strong> (2 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/bench/verilog/tst_bench_top.v<br />~ /trunk/bench/verilog/wb_master_model.v<br /> rherveille Sat, 28 Feb 2004 15:40:42 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=50 Added testbench https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=49 <div><strong>Rev 49 - rherveille</strong> (3 file(s) modified)</div><div>Added testbench</div>+ /trunk/bench/verilog/spi_slave_model.v<br />~ /trunk/bench/verilog/tst_bench_top.v<br />~ /trunk/bench/verilog/wb_master_model.v<br /> rherveille Sat, 28 Feb 2004 15:32:55 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2F&rev=49
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