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i2c
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https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&
Tue, 09 Jun 2026 18:32:31 +0100
FeedCreator 1.7.2
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Updated filter_cnt generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=76
<div><strong>Rev 76 - rherveille</strong> (1 file(s) modified)</div><div>Updated filter_cnt generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Sun, 06 Jun 2010 09:46:45 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=76
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Fixed sSDA generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=75
<div><strong>Rev 75 - rherveille</strong> (1 file(s) modified)</div><div>Fixed sSDA generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Mon, 31 May 2010 13:05:54 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=75
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Added SCL/SDA line filter
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=74
<div><strong>Rev 74 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL/SDA line filter</div>~ /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />
rherveille
Tue, 12 Jan 2010 16:36:48 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=74
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Fixed double wishbone write in a single access
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=73
<div><strong>Rev 73 - rherveille</strong> (1 file(s) modified)</div><div>Fixed double wishbone write in a single access</div>~ /i2c/trunk/rtl/verilog/i2c_master_top.v<br />
rherveille
Tue, 12 Jan 2010 16:35:28 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=73
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Fixed AL generation
Added median filter on SDA and SCL inputs
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=72
<div><strong>Rev 72 - rherveille</strong> (1 file(s) modified)</div><div>Fixed AL generation<br />
Added median filter on SDA and SCL inputs</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Tue, 12 Jan 2010 16:27:06 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=72
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Fixed double wishbone write in a single access
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=71
<div><strong>Rev 71 - rherveille</strong> (1 file(s) modified)</div><div>Fixed double wishbone write in a single access</div>~ /i2c/trunk/rtl/vhdl/i2c_master_top.vhd<br />
rherveille
Tue, 12 Jan 2010 16:25:35 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=71
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=68
<div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 22:30:52 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2F&rev=68
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Fixed slave_wait clocked event syntax
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=67
<div><strong>Rev 67 - rherveille</strong> (1 file(s) modified)</div><div>Fixed slave_wait clocked event syntax</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Wed, 04 Feb 2009 20:17:34 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=67
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Fixed type iscl_oen instead of scl_oen
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=66
<div><strong>Rev 66 - rherveille</strong> (1 file(s) modified)</div><div>Fixed type iscl_oen instead of scl_oen</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Tue, 20 Jan 2009 20:40:36 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=66
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Changed wb_adr_i from unsigned to std_logic_vector
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=65
<div><strong>Rev 65 - rherveille</strong> (1 file(s) modified)</div><div>Changed wb_adr_i from unsigned to std_logic_vector</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />
rherveille
Tue, 20 Jan 2009 10:38:45 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=65
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Added SCL clock synchronization logic
Fixed slave_wait signal generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=64
<div><strong>Rev 64 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL clock synchronization logic<br />
Fixed slave_wait signal generation</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Tue, 20 Jan 2009 10:34:51 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=64
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Added clock synchronization logic
Fixed slave_wait signal
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=63
<div><strong>Rev 63 - rherveille</strong> (1 file(s) modified)</div><div>Added clock synchronization logic<br />
Fixed slave_wait signal</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />
rherveille
Tue, 20 Jan 2009 10:25:29 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=63
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Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=62
<div><strong>Rev 62 - rherveille</strong> (3 file(s) modified)</div><div>Fixed synopsys miss spell (synopsis)<br />
Fixed cr[0] register width<br />
Fixed ! usage ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br />
rherveille
Mon, 19 Jan 2009 20:29:26 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=62
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Added missing semicolons ';' on endif
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=60
<div><strong>Rev 60 - rherveille</strong> (1 file(s) modified)</div><div>Added missing semicolons ';' on endif</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Wed, 11 Oct 2006 12:10:13 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=60
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fixed short scl high pulse after clock stretch
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=59
<div><strong>Rev 59 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Fri, 06 Oct 2006 10:48:24 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=59
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fixed short scl high pulse after clock stretch
fixed slave model ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=57
<div><strong>Rev 57 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch<br />
fixed slave model ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />
rherveille
Mon, 04 Sep 2006 09:08:13 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=57
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Fixed register overwrite issue.
Removed full_case pragma, replaced it by a ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=55
<div><strong>Rev 55 - rherveille</strong> (1 file(s) modified)</div><div>Fixed register overwrite issue.<br />
Removed full_case pragma, replaced it by a ...</div>~ /trunk/rtl/verilog/i2c_master_top.v<br />
rherveille
Sun, 27 Feb 2005 09:26:24 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=55
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Fixed previous fix :) Made a variable vs signal mistake.
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=53
<div><strong>Rev 53 - rherveille</strong> (1 file(s) modified)</div><div>Fixed previous fix :) Made a variable vs signal mistake.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Fri, 07 May 2004 11:53:31 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=53
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Fixed a bug where the core would signal an arbitration ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=52
<div><strong>Rev 52 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would signal an arbitration ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />
rherveille
Fri, 07 May 2004 11:04:00 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=52
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Fixed simulation issue when writing to CR register
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=51
<div><strong>Rev 51 - rherveille</strong> (1 file(s) modified)</div><div>Fixed simulation issue when writing to CR register</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />
rherveille
Sun, 14 Mar 2004 10:17:03 +0100
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Frtl%2F&rev=51
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