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i2c WebSVN RSS feed - i2c https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F& Wed, 01 Dec 2021 06:12:13 +0100 FeedCreator 1.7.2 Added SCL/SDA line filter https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=74 <div><strong>Rev 74 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL/SDA line filter</div>~ /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Tue, 12 Jan 2010 16:36:48 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=74 Fixed double wishbone write in a single access https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=73 <div><strong>Rev 73 - rherveille</strong> (1 file(s) modified)</div><div>Fixed double wishbone write in a single access</div>~ /i2c/trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Tue, 12 Jan 2010 16:35:28 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=73 New directory structure. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=68 <div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 22:30:52 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=68 Added clock synchronization logic Fixed slave_wait signal https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=63 <div><strong>Rev 63 - rherveille</strong> (1 file(s) modified)</div><div>Added clock synchronization logic<br /> Fixed slave_wait signal</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Tue, 20 Jan 2009 10:25:29 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=63 Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=62 <div><strong>Rev 62 - rherveille</strong> (3 file(s) modified)</div><div>Fixed synopsys miss spell (synopsis)<br /> Fixed cr[0] register width<br /> Fixed ! usage ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Mon, 19 Jan 2009 20:29:26 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=62 fixed short scl high pulse after clock stretch fixed slave model ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=57 <div><strong>Rev 57 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch<br /> fixed slave model ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Mon, 04 Sep 2006 09:08:13 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=57 Fixed register overwrite issue. Removed full_case pragma, replaced it by a ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=55 <div><strong>Rev 55 - rherveille</strong> (1 file(s) modified)</div><div>Fixed register overwrite issue.<br /> Removed full_case pragma, replaced it by a ...</div>~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Sun, 27 Feb 2005 09:26:24 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=55 Fixed a bug where the core would signal an arbitration ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=52 <div><strong>Rev 52 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would signal an arbitration ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 07 May 2004 11:04:00 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=52 Fixed a potential bug in the statemachine. During a 'stop' ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=47 <div><strong>Rev 47 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a potential bug in the statemachine. During a 'stop' ...</div>~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br /> rherveille Wed, 18 Feb 2004 11:41:48 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=47 Fix a blocking vs. non-blocking error in the wb_dat output ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=40 <div><strong>Rev 40 - rherveille</strong> (1 file(s) modified)</div><div>Fix a blocking vs. non-blocking error in the wb_dat output ...</div>~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Mon, 01 Sep 2003 10:34:38 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=40 Fixed a bug in the Arbitration Lost generation caused by ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=38 <div><strong>Rev 38 - rherveille</strong> (5 file(s) modified)</div><div>Fixed a bug in the Arbitration Lost generation caused by ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 09 Aug 2003 07:01:33 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=38 Fixed cmd_ack generation item (no bug). https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=36 <div><strong>Rev 36 - rherveille</strong> (1 file(s) modified)</div><div>Fixed cmd_ack generation item (no bug).</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br /> rherveille Mon, 10 Mar 2003 14:26:37 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=36 Fixed a bug where the core would trigger an erroneous ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=35 <div><strong>Rev 35 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would trigger an erroneous ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 05 Feb 2003 00:06:10 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=35 Fixed a bug in the Command Register declaration. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=33 <div><strong>Rev 33 - rherveille</strong> (1 file(s) modified)</div><div>Fixed a bug in the Command Register declaration.</div>~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Thu, 09 Jan 2003 16:44:45 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=33 Small code simplifications https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=30 <div><strong>Rev 30 - rherveille</strong> (2 file(s) modified)</div><div>Small code simplifications</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Thu, 26 Dec 2002 16:05:12 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=30 Core is now a Multimaster I2C controller https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 <div><strong>Rev 29 - rherveille</strong> (3 file(s) modified)</div><div>Core is now a Multimaster I2C controller</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br /> rherveille Thu, 26 Dec 2002 15:02:32 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 Cleaned up code https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=27 <div><strong>Rev 27 - rherveille</strong> (6 file(s) modified)</div><div>Cleaned up code</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 30 Nov 2002 22:24:40 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=27 Fixed some reported minor start/stop generation timing issuess. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=24 <div><strong>Rev 24 - rherveille</strong> (3 file(s) modified)</div><div>Fixed some reported minor start/stop generation timing issuess.</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />+ /trunk/rtl/vhdl/readme<br /> rherveille Wed, 30 Oct 2002 18:10:07 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=24 Fixed a small timing bug in the bit controller.\nAdded verilog ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 <div><strong>Rev 22 - rherveille</strong> (9 file(s) modified)</div><div>Fixed a small timing bug in the bit controller.\nAdded verilog ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />+ /trunk/sim<br />+ /trunk/sim/i2c_verilog<br />+ /trunk/sim/i2c_verilog/run<br />+ /trunk/sim/i2c_verilog/run/bench.vcd<br />+ /trunk/sim/i2c_verilog/run/ncverilog.key<br />+ /trunk/sim/i2c_verilog/run/ncverilog.log<br />+ /trunk/sim/i2c_verilog/run/run<br /> rherveille Sat, 15 Jun 2002 07:37:11 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=22 Changed PRER reset value from 0x0000 to 0xffff, conform specs. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=16 <div><strong>Rev 16 - rherveille</strong> (2 file(s) modified)</div><div>Changed PRER reset value from 0x0000 to 0xffff, conform specs.</div>~ /trunk/rtl/verilog/i2c_master_top.v<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 10 Nov 2001 10:52:55 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fverilog%2F&rev=16
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