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https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&
Wed, 19 Aug 2026 00:26:15 +0100FeedCreator 1.7.2Updated filter_cnt generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=76
<div><strong>Rev 76 - rherveille</strong> (1 file(s) modified)</div><div>Updated filter_cnt generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleSun, 06 Jun 2010 09:46:45 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=76Fixed sSDA generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=75
<div><strong>Rev 75 - rherveille</strong> (1 file(s) modified)</div><div>Fixed sSDA generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleMon, 31 May 2010 13:05:54 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=75Fixed AL generation
Added median filter on SDA and SCL inputs
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=72
<div><strong>Rev 72 - rherveille</strong> (1 file(s) modified)</div><div>Fixed AL generation<br />
Added median filter on SDA and SCL inputs</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleTue, 12 Jan 2010 16:27:06 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=72Fixed double wishbone write in a single access
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=71
<div><strong>Rev 71 - rherveille</strong> (1 file(s) modified)</div><div>Fixed double wishbone write in a single access</div>~ /i2c/trunk/rtl/vhdl/i2c_master_top.vhd<br />rherveilleTue, 12 Jan 2010 16:25:35 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=71New directory structure.
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=68
<div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br />rootMon, 09 Mar 2009 22:30:52 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=68Fixed slave_wait clocked event syntax
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=67
<div><strong>Rev 67 - rherveille</strong> (1 file(s) modified)</div><div>Fixed slave_wait clocked event syntax</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleWed, 04 Feb 2009 20:17:34 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=67Fixed type iscl_oen instead of scl_oen
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=66
<div><strong>Rev 66 - rherveille</strong> (1 file(s) modified)</div><div>Fixed type iscl_oen instead of scl_oen</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleTue, 20 Jan 2009 20:40:36 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=66Changed wb_adr_i from unsigned to std_logic_vector
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=65
<div><strong>Rev 65 - rherveille</strong> (1 file(s) modified)</div><div>Changed wb_adr_i from unsigned to std_logic_vector</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />rherveilleTue, 20 Jan 2009 10:38:45 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=65Added SCL clock synchronization logic
Fixed slave_wait signal generation
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=64
<div><strong>Rev 64 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL clock synchronization logic<br />
Fixed slave_wait signal generation</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleTue, 20 Jan 2009 10:34:51 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=64Added missing semicolons ';' on endif
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=60
<div><strong>Rev 60 - rherveille</strong> (1 file(s) modified)</div><div>Added missing semicolons ';' on endif</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleWed, 11 Oct 2006 12:10:13 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=60fixed short scl high pulse after clock stretch
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=59
<div><strong>Rev 59 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleFri, 06 Oct 2006 10:48:24 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=59Fixed previous fix :) Made a variable vs signal mistake.
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=53
<div><strong>Rev 53 - rherveille</strong> (1 file(s) modified)</div><div>Fixed previous fix :) Made a variable vs signal mistake.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleFri, 07 May 2004 11:53:31 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=53Fixed a bug where the core would signal an arbitration ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=52
<div><strong>Rev 52 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would signal an arbitration ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleFri, 07 May 2004 11:04:00 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=52Fixed simulation issue when writing to CR register
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=51
<div><strong>Rev 51 - rherveille</strong> (1 file(s) modified)</div><div>Fixed simulation issue when writing to CR register</div>~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />rherveilleSun, 14 Mar 2004 10:17:03 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=51Fixed a bug in the arbitration-lost signal generation. VHDL version ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=48
<div><strong>Rev 48 - rherveille</strong> (1 file(s) modified)</div><div>Fixed a bug in the arbitration-lost signal generation. VHDL version ...</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleFri, 27 Feb 2004 07:49:43 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=48Fixed a potential bug in the statemachine. During a 'stop' ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=47
<div><strong>Rev 47 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a potential bug in the statemachine. During a 'stop' ...</div>~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />rherveilleWed, 18 Feb 2004 11:41:48 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=47Forgot an 'end if' :-/
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=39
<div><strong>Rev 39 - rherveille</strong> (1 file(s) modified)</div><div>Forgot an 'end if' :-/</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleTue, 12 Aug 2003 14:48:37 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=39Fixed a bug in the Arbitration Lost generation caused by ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=38
<div><strong>Rev 38 - rherveille</strong> (5 file(s) modified)</div><div>Fixed a bug in the Arbitration Lost generation caused by ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />rherveilleSat, 09 Aug 2003 07:01:33 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=38Fixed a bug where the core would trigger an erroneous ...
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=35
<div><strong>Rev 35 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would trigger an erroneous ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />rherveilleWed, 05 Feb 2003 00:06:10 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=35Fixed a few 'arbitration lost' bugs. VHDL version only.
https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=34
<div><strong>Rev 34 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a few 'arbitration lost' bugs. VHDL version only.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br />rherveilleSat, 01 Feb 2003 02:03:06 +0100https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=34
