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i2c WebSVN RSS feed - i2c https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2Fi2c_master_bit_ctrl.vhd& Mon, 29 Nov 2021 00:05:13 +0100 FeedCreator 1.7.2 Updated filter_cnt generation https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=76 <div><strong>Rev 76 - rherveille</strong> (1 file(s) modified)</div><div>Updated filter_cnt generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Sun, 06 Jun 2010 09:46:45 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=76 Fixed sSDA generation https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=75 <div><strong>Rev 75 - rherveille</strong> (1 file(s) modified)</div><div>Fixed sSDA generation</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Mon, 31 May 2010 13:05:54 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=75 Fixed AL generation Added median filter on SDA and SCL inputs https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=72 <div><strong>Rev 72 - rherveille</strong> (1 file(s) modified)</div><div>Fixed AL generation<br /> Added median filter on SDA and SCL inputs</div>~ /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 12 Jan 2010 16:27:06 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=72 New directory structure. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=68 <div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 22:30:52 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=68 Fixed slave_wait clocked event syntax https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=67 <div><strong>Rev 67 - rherveille</strong> (1 file(s) modified)</div><div>Fixed slave_wait clocked event syntax</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 04 Feb 2009 20:17:34 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=67 Fixed type iscl_oen instead of scl_oen https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=66 <div><strong>Rev 66 - rherveille</strong> (1 file(s) modified)</div><div>Fixed type iscl_oen instead of scl_oen</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 20 Jan 2009 20:40:36 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=66 Added SCL clock synchronization logic Fixed slave_wait signal generation https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=64 <div><strong>Rev 64 - rherveille</strong> (1 file(s) modified)</div><div>Added SCL clock synchronization logic<br /> Fixed slave_wait signal generation</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 20 Jan 2009 10:34:51 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=64 Added missing semicolons ';' on endif https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=60 <div><strong>Rev 60 - rherveille</strong> (1 file(s) modified)</div><div>Added missing semicolons ';' on endif</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 11 Oct 2006 12:10:13 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=60 fixed short scl high pulse after clock stretch https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=59 <div><strong>Rev 59 - rherveille</strong> (1 file(s) modified)</div><div>fixed short scl high pulse after clock stretch</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 06 Oct 2006 10:48:24 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=59 Fixed previous fix :) Made a variable vs signal mistake. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=53 <div><strong>Rev 53 - rherveille</strong> (1 file(s) modified)</div><div>Fixed previous fix :) Made a variable vs signal mistake.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 07 May 2004 11:53:31 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=53 Fixed a bug where the core would signal an arbitration ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=52 <div><strong>Rev 52 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would signal an arbitration ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 07 May 2004 11:04:00 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=52 Fixed a bug in the arbitration-lost signal generation. VHDL version ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=48 <div><strong>Rev 48 - rherveille</strong> (1 file(s) modified)</div><div>Fixed a bug in the arbitration-lost signal generation. VHDL version ...</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Fri, 27 Feb 2004 07:49:43 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=48 Forgot an 'end if' :-/ https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=39 <div><strong>Rev 39 - rherveille</strong> (1 file(s) modified)</div><div>Forgot an 'end if' :-/</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Tue, 12 Aug 2003 14:48:37 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=39 Fixed a bug in the Arbitration Lost generation caused by ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=38 <div><strong>Rev 38 - rherveille</strong> (5 file(s) modified)</div><div>Fixed a bug in the Arbitration Lost generation caused by ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 09 Aug 2003 07:01:33 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=38 Fixed a bug where the core would trigger an erroneous ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=35 <div><strong>Rev 35 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a bug where the core would trigger an erroneous ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br /> rherveille Wed, 05 Feb 2003 00:06:10 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=35 Fixed a few 'arbitration lost' bugs. VHDL version only. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=34 <div><strong>Rev 34 - rherveille</strong> (2 file(s) modified)</div><div>Fixed a few 'arbitration lost' bugs. VHDL version only.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 01 Feb 2003 02:03:06 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=34 Core is now a Multimaster I2C controller. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=31 <div><strong>Rev 31 - rherveille</strong> (3 file(s) modified)</div><div>Core is now a Multimaster I2C controller.</div>~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Thu, 26 Dec 2002 16:05:47 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=31 Cleaned up code https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=27 <div><strong>Rev 27 - rherveille</strong> (6 file(s) modified)</div><div>Cleaned up code</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_byte_ctrl.v<br />~ /trunk/rtl/verilog/i2c_master_top.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd<br />~ /trunk/rtl/vhdl/i2c_master_top.vhd<br /> rherveille Sat, 30 Nov 2002 22:24:40 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=27 Fixed some reported minor start/stop generation timing issuess. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=24 <div><strong>Rev 24 - rherveille</strong> (3 file(s) modified)</div><div>Fixed some reported minor start/stop generation timing issuess.</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />+ /trunk/rtl/vhdl/readme<br /> rherveille Wed, 30 Oct 2002 18:10:07 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=24 Fixed a small timing bug in the bit controller.\nAdded verilog ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=22 <div><strong>Rev 22 - rherveille</strong> (9 file(s) modified)</div><div>Fixed a small timing bug in the bit controller.\nAdded verilog ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />+ /trunk/sim<br />+ /trunk/sim/i2c_verilog<br />+ /trunk/sim/i2c_verilog/run<br />+ /trunk/sim/i2c_verilog/run/bench.vcd<br />+ /trunk/sim/i2c_verilog/run/ncverilog.key<br />+ /trunk/sim/i2c_verilog/run/ncverilog.log<br />+ /trunk/sim/i2c_verilog/run/run<br /> rherveille Sat, 15 Jun 2002 07:37:11 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Frtl%2Fvhdl%2F&rev=22
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