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i2c WebSVN RSS feed - i2c https://opencores.org/websvn//websvn/listing?repname=i2c&path=%2Fi2c%2Ftrunk%2Fsim%2F& Fri, 25 Sep 2020 00:42:30 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Fsim%2F&rev=68 <div><strong>Rev 68 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /i2c<br />+ /i2c/branches<br />+ /i2c/tags<br />+ /i2c/trunk<br />+ /i2c/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 22:30:52 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Fi2c%2Ftrunk%2Fsim%2F&rev=68 Removed synopsys link; it's not used https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Fsim%2F&rev=61 <div><strong>Rev 61 - rherveille</strong> (1 file(s) modified)</div><div>Removed synopsys link; it's not used</div>~ /trunk/sim/i2c_verilog/run/run<br /> rherveille Fri, 06 Apr 2007 09:02:38 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Fsim%2F&rev=61 Fixed a small timing bug in the bit controller.\nAdded verilog ... https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Fsim%2F&rev=22 <div><strong>Rev 22 - rherveille</strong> (9 file(s) modified)</div><div>Fixed a small timing bug in the bit controller.\nAdded verilog ...</div>~ /trunk/rtl/verilog/i2c_master_bit_ctrl.v<br />~ /trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd<br />+ /trunk/sim<br />+ /trunk/sim/i2c_verilog<br />+ /trunk/sim/i2c_verilog/run<br />+ /trunk/sim/i2c_verilog/run/bench.vcd<br />+ /trunk/sim/i2c_verilog/run/ncverilog.key<br />+ /trunk/sim/i2c_verilog/run/ncverilog.log<br />+ /trunk/sim/i2c_verilog/run/run<br /> rherveille Sat, 15 Jun 2002 07:37:11 +0100 https://opencores.org/websvn//websvn/revision?repname=i2c&path=%2Ftrunk%2Fsim%2F&rev=22
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