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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F&
Thu, 16 Apr 2026 23:06:46 +0100
FeedCreator 1.7.2
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1) spi_top.v:
-TX_NEGEDGE bug reported and recommended ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12
<div><strong>Rev 12 - rfajardo</strong> (4 file(s) modified)</div><div>1) spi_top.v:<br />
-TX_NEGEDGE bug reported and recommended ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />
rfajardo
Fri, 30 Oct 2009 18:47:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12
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External interrupt processing was being run multiple times because:
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11
<div><strong>Rev 11 - rfajardo</strong> (2 file(s) modified)</div><div>External interrupt processing was being run multiple times because:<br />
...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sw/support/int.c<br />
rfajardo
Fri, 23 Oct 2009 14:49:17 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11
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Added a file containing models for each FPGA memory instances ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=10
<div><strong>Rev 10 - rfajardo</strong> (7 file(s) modified)</div><div>Added a file containing models for each FPGA memory instances ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/sim_lib<br />+ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />
rfajardo
Fri, 09 Oct 2009 15:20:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=10
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Tiny change to testbench gain:
-uart_srx is ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=9
<div><strong>Rev 9 - rfajardo</strong> (1 file(s) modified)</div><div>Tiny change to testbench gain:<br />
-uart_srx is ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 07 Oct 2009 16:32:49 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=9
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Cosmetic changes to minsoc_bench.v:
-reset and clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=8
<div><strong>Rev 8 - rfajardo</strong> (1 file(s) modified)</div><div>Cosmetic changes to minsoc_bench.v:<br />
-reset and clock ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 07 Oct 2009 16:27:57 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=8
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Some changes:
-wb_cabs removed from minsoc_top.v and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=7
<div><strong>Rev 7 - rfajardo</strong> (6 file(s) modified)</div><div>Some changes:<br />
-wb_cabs removed from minsoc_top.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Fri, 02 Oct 2009 15:56:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=7
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No implementation relevant changes.
Testbench used generic memory from minsoc_onchip_ram.v ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=6
<div><strong>Rev 6 - rfajardo</strong> (3 file(s) modified)</div><div>No implementation relevant changes. <br />
<br />
Testbench used generic memory from minsoc_onchip_ram.v ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />
rfajardo
Mon, 28 Sep 2009 09:37:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=6
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vpi path corrected in how to.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=5
<div><strong>Rev 5 - rfajardo</strong> (2 file(s) modified)</div><div>vpi path corrected in how to.</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Tue, 22 Sep 2009 10:37:24 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=5
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minsoc_bench.v had a big memory declaration to load the firmware, ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=4
<div><strong>Rev 4 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_bench.v had a big memory declaration to load the firmware, ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />- /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Tue, 22 Sep 2009 10:23:31 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=4
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Changed documentation
-advice to compile sw/utils before ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=3
<div><strong>Rev 3 - rfajardo</strong> (2 file(s) modified)</div><div>Changed documentation<br />
-advice to compile sw/utils before ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Fri, 18 Sep 2009 12:15:46 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=3
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First commit of project. Beta status:
-testbench: ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=2
<div><strong>Rev 2 - rfajardo</strong> (92 file(s) modified)</div><div>First commit of project. Beta status:<br />
-testbench: ...</div>+ /minsoc/trunk/backend<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/bench<br />+ /minsoc/trunk/bench/verilog<br />+ /minsoc/trunk/bench/verilog/eth_phy.v<br />+ /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />+ /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />+ /minsoc/trunk/bench/verilog/vpi<br />+ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />+ /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />+ /minsoc/trunk/doc<br />+ /minsoc/trunk/doc/lgpl-3.0.txt<br />+ /minsoc/trunk/doc/minsoc.odt<br />+ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/rtl<br />+ /minsoc/trunk/rtl/verilog<br />+ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/OR1K_startup_generic.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_clgen.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_shift.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />+ /minsoc/trunk/sim<br />+ /minsoc/trunk/sim/bin<br />+ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />+ /minsoc/trunk/sim/results<br />+ /minsoc/trunk/sim/results/wave.do.sav<br />+ /minsoc/trunk/sim/run<br />+ /minsoc/trunk/sim/run/generate_bench<br />+ /minsoc/trunk/sim/run/run_bench<br />+ /minsoc/trunk/sim/run/start_server<br />+ /minsoc/trunk/sw<br />+ /minsoc/trunk/sw/eth<br />+ /minsoc/trunk/sw/eth/eth.c<br />+ /minsoc/trunk/sw/eth/eth.h<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/support<br />+ /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/except.S<br />+ /minsoc/trunk/sw/support/int.c<br />+ /minsoc/trunk/sw/support/int.h<br />+ /minsoc/trunk/sw/support/Makefile<br />+ /minsoc/trunk/sw/support/Makefile.inc<br />+ /minsoc/trunk/sw/support/mc.h<br />+ /minsoc/trunk/sw/support/orp.cfg<br />+ /minsoc/trunk/sw/support/orp.ld<br />+ /minsoc/trunk/sw/support/reset.S<br />+ /minsoc/trunk/sw/support/spr_defs.h<br />+ /minsoc/trunk/sw/support/support.c<br />+ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/uart.c<br />+ /minsoc/trunk/sw/support/uart.h<br />+ /minsoc/trunk/sw/support/vfnprintf.c<br />+ /minsoc/trunk/sw/support/vfnprintf.h<br />+ /minsoc/trunk/sw/uart<br />+ /minsoc/trunk/sw/uart/Makefile<br />+ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/sw/uart/uart.h<br />+ /minsoc/trunk/sw/utils<br />+ /minsoc/trunk/sw/utils/bin2c.c<br />+ /minsoc/trunk/sw/utils/bin2flimg.c<br />+ /minsoc/trunk/sw/utils/bin2hex.c<br />+ /minsoc/trunk/sw/utils/bin2srec.c<br />+ /minsoc/trunk/sw/utils/bin2vmem.c<br />+ /minsoc/trunk/sw/utils/loader.c<br />+ /minsoc/trunk/sw/utils/Makefile<br />+ /minsoc/trunk/sw/utils/marksec<br />+ /minsoc/trunk/sw/utils/merge2srec<br />+ /minsoc/trunk/sw/utils/or32-idecode<br />+ /minsoc/trunk/sw/utils/or32-idecode/ansidecl.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/bfd.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/dis-asm.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/example_input<br />+ /minsoc/trunk/sw/utils/or32-idecode/Makefile<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-dis.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-opc.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/symcat.h<br />
rfajardo
Fri, 18 Sep 2009 11:46:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=2
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The project was created and the structure was created
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=1
<div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project was created and the structure was created</div>+ /minsoc<br />+ /minsoc/branches<br />+ /minsoc/tags<br />+ /minsoc/trunk<br />
root
Fri, 18 Sep 2009 10:10:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=1
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