OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Error creating feed file, please check write permissions.
minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F& Tue, 27 Oct 2020 11:59:35 +0100 FeedCreator 1.7.2 Removing bugs introduced when splitting clocks and reset. ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=129 <div><strong>Rev 129 - rfajardo</strong> (2 file(s) modified)</div><div>Removing bugs introduced when splitting clocks and reset. <br /> ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br /> rfajardo Thu, 03 Nov 2011 00:31:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=129 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=128 <div><strong>Rev 128 - rfajardo</strong> (3 file(s) modified)</div><div>Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br /> rfajardo Wed, 02 Nov 2011 23:46:04 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=128 Removing redundant simulation output. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=127 <div><strong>Rev 127 - rfajardo</strong> (1 file(s) modified)</div><div>Removing redundant simulation output.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:38:45 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=127 Updating information about simulation time for Ethernet test. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=126 <div><strong>Rev 126 - rfajardo</strong> (1 file(s) modified)</div><div>Updating information about simulation time for Ethernet test.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:36:33 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=126 Adjusting testbench messages. Creating tasks for firmware tests. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=125 <div><strong>Rev 125 - rfajardo</strong> (1 file(s) modified)</div><div>Adjusting testbench messages. Creating tasks for firmware tests.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:19:19 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=125 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=124 <div><strong>Rev 124 - rfajardo</strong> (6 file(s) modified)</div><div>Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 15:27:24 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=124 Renaming reg final to firmware_size. Final is a keyword for ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=123 <div><strong>Rev 123 - rfajardo</strong> (1 file(s) modified)</div><div>Renaming reg final to firmware_size. Final is a keyword for ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 10:39:00 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=123 Renaming minsoc-configure.sh to minsoc-setup.sh. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=122 <div><strong>Rev 122 - rfajardo</strong> (2 file(s) modified)</div><div>Renaming minsoc-configure.sh to minsoc-setup.sh.</div>- /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-setup.sh<br /> rfajardo Thu, 27 Oct 2011 21:12:31 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=122 Asserting svn:executable properties of modelsim/*.bat scripts. Including corrected patch for ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=121 <div><strong>Rev 121 - rfajardo</strong> (7 file(s) modified)</div><div>Asserting svn:executable properties of modelsim/*.bat scripts. <br /> <br /> Including corrected patch for ...</div>~ /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/syn/xilinx/setup.bat<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/or1200v1_hwbkpt.patch<br />~ /minsoc/branches/rc-1.0/utils/setup/required-cygwin-tools.txt<br /> rfajardo Thu, 27 Oct 2011 19:39:23 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=121 ethmac.prj: a file was missing https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=120 <div><strong>Rev 120 - rfajardo</strong> (1 file(s) modified)</div><div>ethmac.prj: a file was missing</div>~ /minsoc/branches/rc-1.0/prj/src/ethmac.prj<br /> rfajardo Thu, 27 Oct 2011 16:49:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=120 Tricking Subversion to accept bat files that are now executable. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=119 <div><strong>Rev 119 - rfajardo</strong> (4 file(s) modified)</div><div>Tricking Subversion to accept bat files that are now executable.</div>~ /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/syn/xilinx/setup.bat<br /> rfajardo Thu, 27 Oct 2011 16:19:08 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=119 Configure scripts for Xilinx devices updated. All of them require ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=118 <div><strong>Rev 118 - rfajardo</strong> (4 file(s) modified)</div><div>Configure scripts for Xilinx devices updated. All of them require ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br /> rfajardo Thu, 27 Oct 2011 16:16:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=118 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=117 <div><strong>Rev 117 - rfajardo</strong> (2 file(s) modified)</div><div>spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br /> rfajardo Thu, 27 Oct 2011 15:27:12 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=117 Configure scripts were trying to copy/patch projects files before creating ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=116 <div><strong>Rev 116 - rfajardo</strong> (5 file(s) modified)</div><div>Configure scripts were trying to copy/patch projects files before creating ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/branches/rc-1.0/backend/std/configure<br /> rfajardo Thu, 27 Oct 2011 14:53:51 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=116 configure.sh script dir aware. minsoc-install.sh logging to script dir. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=115 <div><strong>Rev 115 - rfajardo</strong> (2 file(s) modified)</div><div>configure.sh script dir aware.<br /> minsoc-install.sh logging to script dir.</div>~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 27 Oct 2011 14:18:41 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=115 Installation and Configuration scripts can be run out of any ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=114 <div><strong>Rev 114 - rfajardo</strong> (3 file(s) modified)</div><div>Installation and Configuration scripts can be run out of any ...</div>~ /minsoc/branches/rc-1.0/utils/setup/beautify.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 27 Oct 2011 13:58:39 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=114 minsoc-install.sh &amp; minsoc-configure.sh: -aware of location ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=113 <div><strong>Rev 113 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc-install.sh &amp; minsoc-configure.sh: <br /> -aware of location ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />~ /minsoc/branches/rc-1.0/prj/src/blackboxes/or1200_top.v<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 27 Oct 2011 13:49:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=113 Updating installation &amp; configuration scripts. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=112 <div><strong>Rev 112 - rfajardo</strong> (3 file(s) modified)</div><div>Updating installation &amp; configuration scripts.</div>~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 22:43:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=112 minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=111 <div><strong>Rev 111 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc-install.sh: DIR_TO_INSTALL is required before using beautify.sh</div>~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 21:49:56 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=111 Fixing several minor issues with the system: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=110 <div><strong>Rev 110 - rfajardo</strong> (13 file(s) modified)</div><div>Fixing several minor issues with the system:<br /> ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />- /minsoc/branches/rc-1.0/prj/scripts/altprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvprj.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh<br />~ /minsoc/branches/rc-1.0/prj/src/or1200_top.prj<br />~ /minsoc/branches/rc-1.0/rtl/verilog<br />+ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 21:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=110
© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.