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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F&
Thu, 28 Mar 2024 10:48:22 +0100
FeedCreator 1.7.2
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Updating configure scripts. Calling make into the right directories now.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=144
<div><strong>Rev 144 - rfajardo</strong> (5 file(s) modified)</div><div>Updating configure scripts. Calling make into the right directories now.</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />
rfajardo
Tue, 22 Nov 2011 11:03:57 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=144
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Compiling firmwares in board configuration scripts instead of on global ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=143
<div><strong>Rev 143 - rfajardo</strong> (5 file(s) modified)</div><div>Compiling firmwares in board configuration scripts instead of on global ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/std/configure<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />
rfajardo
Tue, 22 Nov 2011 10:59:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=143
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Updating configure.sh:
1) we don't patch ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=142
<div><strong>Rev 142 - rfajardo</strong> (6 file(s) modified)</div><div>Updating configure.sh: <br />
1) we don't patch ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/utils/setup/configure.sh<br />
rfajardo
Tue, 22 Nov 2011 10:54:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=142
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Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=141
<div><strong>Rev 141 - rfajardo</strong> (32 file(s) modified)</div><div>Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ...</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />/minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/scripts/altvhdprj.sh<br />+ /minsoc/trunk/prj/scripts/altvprj.sh<br />~ /minsoc/trunk/prj/scripts/simverilog.sh<br />~ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/src/ethmac.prj<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.sh<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/utils/bin2hex.c<br />~ /minsoc/trunk/syn/xilinx/setup.bat<br />~ /minsoc/trunk/utils/setup/beautify.sh<br />+ /minsoc/trunk/utils/setup/configure.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />+ /minsoc/trunk/utils/setup/minsoc-setup.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br />
rfajardo
Tue, 22 Nov 2011 10:46:40 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=141
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Including required modules for verilator simulation.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=140
<div><strong>Rev 140 - rfajardo</strong> (7 file(s) modified)</div><div>Including required modules for verilator simulation.</div>+ /minsoc/branches/verilator/bench/verilator<br />+ /minsoc/branches/verilator/bench/verilator/minsoc_bench_core.v<br />+ /minsoc/branches/verilator/bench/verilator/verilator_defines.v<br />~ /minsoc/branches/verilator/rtl/verilog/minsoc_top.v<br />+ /minsoc/branches/verilator/sim/verilator<br />+ /minsoc/branches/verilator/sim/verilator/generate_verilator_bench<br />+ /minsoc/branches/verilator/sim/verilator/run_verilator_bench<br />
rfajardo
Tue, 22 Nov 2011 10:11:38 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=140
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Creating a verilator branche.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=139
<div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br />
rfajardo
Tue, 22 Nov 2011 10:09:55 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=139
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DIR_TO_INSTALL creation using wizard
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=138
<div><strong>Rev 138 - ConX.</strong> (1 file(s) modified)</div><div>DIR_TO_INSTALL creation using wizard</div>~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />
ConX.
Mon, 21 Nov 2011 21:37:56 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=138
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Removing uncomplete support for ml509 and not working support for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=137
<div><strong>Rev 137 - rfajardo</strong> (2 file(s) modified)</div><div>Removing uncomplete support for ml509 and not working support for ...</div>- /minsoc/branches/rc-1.0/backend/ml509<br />- /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth<br />
rfajardo
Mon, 21 Nov 2011 10:45:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=137
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Installation on Ubuntu-11.10 has shown that a binary called makeinfo ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=136
<div><strong>Rev 136 - rfajardo</strong> (1 file(s) modified)</div><div>Installation on Ubuntu-11.10 has shown that a binary called makeinfo ...</div>~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />
rfajardo
Mon, 14 Nov 2011 15:14:41 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=136
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Installation on Ubuntu-11.10 has shown that package texinfo is required ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=135
<div><strong>Rev 135 - rfajardo</strong> (1 file(s) modified)</div><div>Installation on Ubuntu-11.10 has shown that package texinfo is required ...</div>~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />
rfajardo
Mon, 14 Nov 2011 15:12:40 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=135
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run_sim.bat for ModelSim updated to acquire the firmware_size for command ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=134
<div><strong>Rev 134 - rfajardo</strong> (1 file(s) modified)</div><div>run_sim.bat for ModelSim updated to acquire the firmware_size for command ...</div>~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />
rfajardo
Mon, 07 Nov 2011 11:14:41 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=134
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Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=133
<div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br />
rfajardo
Mon, 07 Nov 2011 09:48:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=133
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ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=132
<div><strong>Rev 132 - rfajardo</strong> (2 file(s) modified)</div><div>ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.</div>~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />
rfajardo
Thu, 03 Nov 2011 14:10:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=132
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Renaming testbench modules. Adding to ifdefs without which the testbench ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=131
<div><strong>Rev 131 - rfajardo</strong> (4 file(s) modified)</div><div>Renaming testbench modules. Adding to ifdefs without which the testbench ...</div>- /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />
rfajardo
Thu, 03 Nov 2011 13:58:53 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=131
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minsoc_bench.v: task test_eth has to be phased out together with ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=130
<div><strong>Rev 130 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc_bench.v: task test_eth has to be phased out together with ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />
rfajardo
Thu, 03 Nov 2011 11:39:30 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=130
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Removing bugs introduced when splitting clocks and reset.
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=129
<div><strong>Rev 129 - rfajardo</strong> (2 file(s) modified)</div><div>Removing bugs introduced when splitting clocks and reset. <br />
...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />
rfajardo
Thu, 03 Nov 2011 00:31:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=129
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Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=128
<div><strong>Rev 128 - rfajardo</strong> (3 file(s) modified)</div><div>Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />
rfajardo
Wed, 02 Nov 2011 23:46:04 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=128
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Removing redundant simulation output.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=127
<div><strong>Rev 127 - rfajardo</strong> (1 file(s) modified)</div><div>Removing redundant simulation output.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 02 Nov 2011 17:38:45 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=127
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Updating information about simulation time for Ethernet test.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=126
<div><strong>Rev 126 - rfajardo</strong> (1 file(s) modified)</div><div>Updating information about simulation time for Ethernet test.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 02 Nov 2011 17:36:33 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=126
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Adjusting testbench messages. Creating tasks for firmware tests.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=125
<div><strong>Rev 125 - rfajardo</strong> (1 file(s) modified)</div><div>Adjusting testbench messages. Creating tasks for firmware tests.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 02 Nov 2011 17:19:19 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=125
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