URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Error creating feed file, please check write permissions.
minsoc
WebSVN RSS feed - minsoc
https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F&
Fri, 29 Mar 2024 08:49:26 +0100
FeedCreator 1.7.2
-
Paragraph minor changes, used in announcement and double checked.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=23
<div><strong>Rev 23 - rfajardo</strong> (2 file(s) modified)</div><div>Paragraph minor changes, used in announcement and double checked.</div>~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />
rfajardo
Thu, 28 Jan 2010 16:41:57 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=23
-
Status progress and howto pdf documents were not commited, there ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=22
<div><strong>Rev 22 - rfajardo</strong> (2 file(s) modified)</div><div>Status progress and howto pdf documents were not commited, there ...</div>+ /minsoc/trunk/doc/howto.pdf<br />+ /minsoc/trunk/doc/status_progress.pdf<br />
rfajardo
Thu, 28 Jan 2010 15:43:17 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=22
-
Including the first draft project documentation. How to and status ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=21
<div><strong>Rev 21 - rfajardo</strong> (9 file(s) modified)</div><div>Including the first draft project documentation. How to and status ...</div>- /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/doc/src<br />+ /minsoc/trunk/doc/src/figures<br />+ /minsoc/trunk/doc/src/figures/or1200.gif<br />+ /minsoc/trunk/doc/src/figures/soc.odg<br />+ /minsoc/trunk/doc/src/howto.odt<br />+ /minsoc/trunk/doc/src/minsoc.odt<br />+ /minsoc/trunk/doc/src/status_progress.odt<br />
rfajardo
Thu, 28 Jan 2010 14:31:12 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=21
-
minsoc_defines.v had a semicolon at the end of the two ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=20
<div><strong>Rev 20 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_defines.v had a semicolon at the end of the two ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Thu, 21 Jan 2010 13:57:46 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=20
-
Documentation update. How To: 7) Examples:
-Spartan ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=19
<div><strong>Rev 19 - rfajardo</strong> (2 file(s) modified)</div><div>Documentation update. How To: 7) Examples:<br />
-Spartan ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Mon, 21 Dec 2009 09:58:58 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=19
-
Deprecated comments removed from the file listing files.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=18
<div><strong>Rev 18 - rfajardo</strong> (2 file(s) modified)</div><div>Deprecated comments removed from the file listing files.</div>~ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model.txt<br />
rfajardo
Thu, 19 Nov 2009 09:43:09 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=18
-
Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=17
<div><strong>Rev 17 - rfajardo</strong> (16 file(s) modified)</div><div>Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...</div>- /minsoc/trunk/bench/verilog/eth_phy.v<br />- /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />- /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br />
rfajardo
Tue, 17 Nov 2009 14:38:49 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=17
-
Further initialization improvement of non-used signals, setting interrupt signals to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=16
<div><strong>Rev 16 - rfajardo</strong> (1 file(s) modified)</div><div>Further initialization improvement of non-used signals, setting interrupt signals to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Thu, 12 Nov 2009 11:04:14 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=16
-
Including verified pinout for external spi flash on spartan3a dsp ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=15
<div><strong>Rev 15 - rfajardo</strong> (1 file(s) modified)</div><div>Including verified pinout for external spi flash on spartan3a dsp ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />
rfajardo
Wed, 11 Nov 2009 17:28:19 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=15
-
Wishbone error signal of Ethernet core was not tied to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=14
<div><strong>Rev 14 - rfajardo</strong> (1 file(s) modified)</div><div>Wishbone error signal of Ethernet core was not tied to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Tue, 03 Nov 2009 10:22:29 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=14
-
Updating spartan3e_starter_kit.ucf so that it does not deliver errors on ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=13
<div><strong>Rev 13 - rfajardo</strong> (1 file(s) modified)</div><div>Updating spartan3e_starter_kit.ucf so that it does not deliver errors on ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />
rfajardo
Mon, 02 Nov 2009 09:59:46 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=13
-
1) spi_top.v:
-TX_NEGEDGE bug reported and recommended ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12
<div><strong>Rev 12 - rfajardo</strong> (4 file(s) modified)</div><div>1) spi_top.v:<br />
-TX_NEGEDGE bug reported and recommended ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />
rfajardo
Fri, 30 Oct 2009 18:47:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12
-
External interrupt processing was being run multiple times because:
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11
<div><strong>Rev 11 - rfajardo</strong> (2 file(s) modified)</div><div>External interrupt processing was being run multiple times because:<br />
...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sw/support/int.c<br />
rfajardo
Fri, 23 Oct 2009 14:49:17 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11
-
Added a file containing models for each FPGA memory instances ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=10
<div><strong>Rev 10 - rfajardo</strong> (7 file(s) modified)</div><div>Added a file containing models for each FPGA memory instances ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/sim_lib<br />+ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />
rfajardo
Fri, 09 Oct 2009 15:20:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=10
-
Tiny change to testbench gain:
-uart_srx is ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=9
<div><strong>Rev 9 - rfajardo</strong> (1 file(s) modified)</div><div>Tiny change to testbench gain:<br />
-uart_srx is ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 07 Oct 2009 16:32:49 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=9
-
Cosmetic changes to minsoc_bench.v:
-reset and clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=8
<div><strong>Rev 8 - rfajardo</strong> (1 file(s) modified)</div><div>Cosmetic changes to minsoc_bench.v:<br />
-reset and clock ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 07 Oct 2009 16:27:57 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=8
-
Some changes:
-wb_cabs removed from minsoc_top.v and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=7
<div><strong>Rev 7 - rfajardo</strong> (6 file(s) modified)</div><div>Some changes:<br />
-wb_cabs removed from minsoc_top.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Fri, 02 Oct 2009 15:56:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=7
-
No implementation relevant changes.
Testbench used generic memory from minsoc_onchip_ram.v ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=6
<div><strong>Rev 6 - rfajardo</strong> (3 file(s) modified)</div><div>No implementation relevant changes. <br />
<br />
Testbench used generic memory from minsoc_onchip_ram.v ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />
rfajardo
Mon, 28 Sep 2009 09:37:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=6
-
vpi path corrected in how to.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=5
<div><strong>Rev 5 - rfajardo</strong> (2 file(s) modified)</div><div>vpi path corrected in how to.</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Tue, 22 Sep 2009 10:37:24 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=5
-
minsoc_bench.v had a big memory declaration to load the firmware, ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=4
<div><strong>Rev 4 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_bench.v had a big memory declaration to load the firmware, ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />- /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />
rfajardo
Tue, 22 Sep 2009 10:23:31 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=4
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.