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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F&
Thu, 28 Mar 2024 22:22:50 +0100FeedCreator 1.7.2minsoc SoC documentation had 2 small typo corrections. Performance penalty ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=30
<div><strong>Rev 30 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc SoC documentation had 2 small typo corrections. Performance penalty ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />~ /minsoc/trunk/sim/run/generate_bench<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sim/run/start_server<br />rfajardoThu, 17 Jun 2010 09:54:28 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=30Finishing the howto for Spartan3E Starter Kit with Ethernet. Last ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=29
<div><strong>Rev 29 - rfajardo</strong> (2 file(s) modified)</div><div>Finishing the howto for Spartan3E Starter Kit with Ethernet. Last ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />rfajardoThu, 06 May 2010 10:25:23 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=291) Period calculations through 1/freq on testbench use now a ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=28
<div><strong>Rev 28 - rfajardo</strong> (4 file(s) modified)</div><div>1) Period calculations through 1/freq on testbench use now a ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />rfajardoWed, 05 May 2010 14:50:01 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=28Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=27
<div><strong>Rev 27 - rfajardo</strong> (1 file(s) modified)</div><div>Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ...</div>~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />rfajardoTue, 20 Apr 2010 14:14:15 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=27On version 34 of the Advanced Debug System the signal ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=26
<div><strong>Rev 26 - rfajardo</strong> (1 file(s) modified)</div><div>On version 34 of the Advanced Debug System the signal ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />rfajardoSun, 11 Apr 2010 01:32:44 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=26Updated the howto document to adapt minsoc to a new ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=25
<div><strong>Rev 25 - rfajardo</strong> (2 file(s) modified)</div><div>Updated the howto document to adapt minsoc to a new ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />rfajardoTue, 06 Apr 2010 09:39:40 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=25E-mail in the documentation has been corrected.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=24
<div><strong>Rev 24 - rfajardo</strong> (2 file(s) modified)</div><div>E-mail in the documentation has been corrected.</div>~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />rfajardoMon, 01 Feb 2010 21:09:36 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=24Paragraph minor changes, used in announcement and double checked.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=23
<div><strong>Rev 23 - rfajardo</strong> (2 file(s) modified)</div><div>Paragraph minor changes, used in announcement and double checked.</div>~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />rfajardoThu, 28 Jan 2010 16:41:57 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=23Status progress and howto pdf documents were not commited, there ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=22
<div><strong>Rev 22 - rfajardo</strong> (2 file(s) modified)</div><div>Status progress and howto pdf documents were not commited, there ...</div>+ /minsoc/trunk/doc/howto.pdf<br />+ /minsoc/trunk/doc/status_progress.pdf<br />rfajardoThu, 28 Jan 2010 15:43:17 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=22Including the first draft project documentation. How to and status ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=21
<div><strong>Rev 21 - rfajardo</strong> (9 file(s) modified)</div><div>Including the first draft project documentation. How to and status ...</div>- /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/doc/src<br />+ /minsoc/trunk/doc/src/figures<br />+ /minsoc/trunk/doc/src/figures/or1200.gif<br />+ /minsoc/trunk/doc/src/figures/soc.odg<br />+ /minsoc/trunk/doc/src/howto.odt<br />+ /minsoc/trunk/doc/src/minsoc.odt<br />+ /minsoc/trunk/doc/src/status_progress.odt<br />rfajardoThu, 28 Jan 2010 14:31:12 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=21minsoc_defines.v had a semicolon at the end of the two ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=20
<div><strong>Rev 20 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_defines.v had a semicolon at the end of the two ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />rfajardoThu, 21 Jan 2010 13:57:46 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=20Documentation update. How To: 7) Examples:
-Spartan ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=19
<div><strong>Rev 19 - rfajardo</strong> (2 file(s) modified)</div><div>Documentation update. How To: 7) Examples:<br />
-Spartan ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />rfajardoMon, 21 Dec 2009 09:58:58 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=19Deprecated comments removed from the file listing files.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=18
<div><strong>Rev 18 - rfajardo</strong> (2 file(s) modified)</div><div>Deprecated comments removed from the file listing files.</div>~ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model.txt<br />rfajardoThu, 19 Nov 2009 09:43:09 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=18Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=17
<div><strong>Rev 17 - rfajardo</strong> (16 file(s) modified)</div><div>Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...</div>- /minsoc/trunk/bench/verilog/eth_phy.v<br />- /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />- /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br />rfajardoTue, 17 Nov 2009 14:38:49 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=17Further initialization improvement of non-used signals, setting interrupt signals to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=16
<div><strong>Rev 16 - rfajardo</strong> (1 file(s) modified)</div><div>Further initialization improvement of non-used signals, setting interrupt signals to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />rfajardoThu, 12 Nov 2009 11:04:14 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=16Including verified pinout for external spi flash on spartan3a dsp ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=15
<div><strong>Rev 15 - rfajardo</strong> (1 file(s) modified)</div><div>Including verified pinout for external spi flash on spartan3a dsp ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />rfajardoWed, 11 Nov 2009 17:28:19 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=15Wishbone error signal of Ethernet core was not tied to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=14
<div><strong>Rev 14 - rfajardo</strong> (1 file(s) modified)</div><div>Wishbone error signal of Ethernet core was not tied to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />rfajardoTue, 03 Nov 2009 10:22:29 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=14Updating spartan3e_starter_kit.ucf so that it does not deliver errors on ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=13
<div><strong>Rev 13 - rfajardo</strong> (1 file(s) modified)</div><div>Updating spartan3e_starter_kit.ucf so that it does not deliver errors on ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />rfajardoMon, 02 Nov 2009 09:59:46 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=131) spi_top.v:
-TX_NEGEDGE bug reported and recommended ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12
<div><strong>Rev 12 - rfajardo</strong> (4 file(s) modified)</div><div>1) spi_top.v:<br />
-TX_NEGEDGE bug reported and recommended ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />rfajardoFri, 30 Oct 2009 18:47:37 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=12External interrupt processing was being run multiple times because:
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11
<div><strong>Rev 11 - rfajardo</strong> (2 file(s) modified)</div><div>External interrupt processing was being run multiple times because:<br />
...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sw/support/int.c<br />rfajardoFri, 23 Oct 2009 14:49:17 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=11